profile

Dr. Ashwani Kumar Rana

Associate Professor

Dr. Ashwani K. Rana was born in Kangra, H.P., India in 1974. He received his B.Tech degree in Electronics and Communication Engineering from National Institute of Technology, Hamirpur, India and M.Tech degree in VLSI Technology from Indian Institute of Technology, Roorkee, India. He did his the Ph.D degree from National Institute of Technology, Hamirpur, India in the field of Nano Devices Presently he is with Department of Electronics and Communication Engineering, National Institute of Technology, Hamirpur, India, as an Associate Professor. His research interest include modeling of semiconductor devices, low power high performance VLSI circuit design and emerging integrated circuit technologies. He has guided 05 Ph.Ds and 03 are ongoing in these areas He has more than 80 publications in International/National Journal & conferences and guided more than 50 M.Tech students in these areas. He is member of ISTE and prant president of Vigyan Bharti

Name : Dr. Ashwani Kumar Rana
Designation : Associate Professor
Department : Electronics & Communication Engineering
Qualification : B.Tech(NIT H) , M.Tech(IIT Roorkee) , Ph.D (NIT H)
Phone : 254638
Email ID : ashwani@nith.ac.in
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General Information



Name : Dr. Ashwani Kumar Rana
Designation : Associate Professor
Department : Electronics & Communication Engineering
Qualification : B.Tech(NIT H) , M.Tech(IIT Roorkee) , Ph.D (NIT H)
Date of Birth : 05/23/1974
Date of joining : 08/22/2000

Contact Details

Phone : 254638
Email ID : ashwani@nith.ac.in

Specialization

Position Held



Position Department Name Institute Name Time Period

Educational Qualification



Name of the Degree Year of Passing Institute/University
B.Tech (Electronics and Communication Engineering) 1998 NIT Hamirpur (H.P.)
M.Tech. (VLSI Design, Nano Device Modeling) 2006 IIT Roorkee (U.K.)
Ph.D ( VLSI Device Modeling) 2011 NIT Hamirpur (H.P.)

Honors & Recognitions Achieved



Sr.No. Title Activity Given By Year

Research Experience



Research Interests : Low Power VLSI Design, Nano Device Modeling, Sensor
Brief Research Statement : 1. To create a research base for the academic development of the students as well as concomitant growth of the students. 2. To expose students to industry to understand the dynamics of industry in term of research challenges. 3. To complete the research/ sponsored projects undertaken. 4. Periodical mentoring of students for a purposeful relationship and mutual research growth. 1. To exposing myself to a variety of things (academic and research) so as to achieve a career which is both rewarding and satisfying. 2. To create world class state-of-the-art facilities and ambience in the department. 3. To develop sensitivity as responsible citizen by introducing research progammes for the development of community.

Journal Publications



Year Author(s) Title & Vol. No. Journal Name Indexing (SCI) Web of Science/Scopus
2007 Ashwani K. Rana and S.Dasgupta Unified Compact Modeling of a gate Tunneling Current considering Image Force Induced Barrier Lowering for a nanoscale N-MOSFET and Vol. 4, No. 3, pp. 482-487 Journal of Computational and Theoretical Nanoscience (CTN) SCOPUS
2007 Ashwani K. Rana and S.Dasgupta Analytic Modeling of Non-Uniform Graded Dopant Profile of Polysilicon Gate in Gate Tunneling Current for N-MOSFET in Nanoscale Regime and Vol. 4, No. 1, pp. 179-185 Journal of Computational and Theoretical Nanoscience (CTN) SCOPUS
2008 Ashwani K. Rana and S.Dasgupta Gate Leakage Power analysis for a Nanoscale N-MOSFET and Vol. 5, No. 11, pp. 2180-2185 Journal of Computational and Theoretical Nanoscience (CTN), SCOPUS
2009 Ashwani K. Rana, Shashi B. Rana Anjna Kumari, Vaishnav Kiran Significance of Nanotechnology in construction Engineering and Vol. 1, No. 4, pp. 46-48 International Journal of Recent trends in Engineering Web of Science
2009 Ashwani K. Rana, Narottam Chand and Vinod Kapoor Trap Assisted Tunneling Model for Gate Current in Nano Scale MOSFET with High-K Gate Dielectrics and Vol. 3, No. 7, pp. 402-409 International Journal of Electrical and Electronics Engineering Web of Science
2009 Ashwani K. Rana, Narottam Chand and Vinod Kapoor Gate Tunnel Current Calculation for N-MOSFET Based on Deep Sub-Micron Effects and Vol. 3, No. 7, pp. 426-434 International Journal of Electrical and Electronics Engineering Web of Science
2010 Ashwani K. Rana, Narottam Chand and Vinod Kapoor Analytical Gate Current Modeling in Nano Scale MOSFET with High-k Gate Stack Structure and Vol. 3, No. 2, pp. 169-174 Journal of Electrical and Electronics Engineering Web of Science
2010 Ashwani K. Rana, Narottam Chand and Vinod Kapoor Gate Current Modeling and Optimization of High-k Gate Stack MOSFET Structure in Nano Scale Regime and Vol. 1, No. 3, pp. 253-267 International Journal of Micro-Nano Scale Transport Web of Science
2010 Ashwani K. Rana, Narottam Chand and Vinod Kapoor Impact of Gate Engineering on Gate Leakage Behavior of Nano Scale MOSFETs with High-k Dielectrics and Vol. 5, No. 3, pp. 343-348 Journal of Nanoelectronics and Optoelectronics SCIE
2010 Ashwani K. Rana, Narottam Chand and Vinod Kapoor Gate Leakage Reduction through the use of Source/Drain-to-Gate Non-overlapped MOSFET Structure and Vol. 224, No. 4, pp. 173-181 Journal of Nanoengineering and Nanosystems Web of Science
2011 Ashwani K. Rana, Narottam Chand and Vinod Kapoor Analysis and Application of Hybrid MOSFET Structure for Low Gate Leakage,” Journal of Engineering and Applied Science, Vol. 6, No. 1, pp. 38-46 Journal of Engineering and Applied Science Web of Science
2011 Ashwani K. Rana, Narottam Chand and Vinod Kapoor Gate Leakage Behavior of Source/Drain-to-gate Non-overlapped MOSFET Structure and Vol. 10, No. 1-2, pp. 222-228 Journal of Computational Electronics SCI
2011 Ashwani K. Rana, Narottam Chand and Vinod Kapoor Gate Current Modeling and Optimal Design of Nanoscale Non-Overlapped Gate to Source/Drain MOSFET, and Vol. 32, No. 7, pp. 074001-6 Journal of Semiconductors SCIE
2011 Ashwani K. Rana, Narottam Chand and Vinod Kapoor Modeling Gate Current of Nano Scale MOSFET for Circuit Simulation and Vol. 7, No. 2, pp. 115-130 Multidiscipline Modeling in Materials and Structures SCOPUS
2011 Ashwani K. Rana, Narottam Chand and Vinod Kapoor Gate Leakage Aware Optimal Design of Modified Hybrid Nanoscale MOSFET and Its Application to Logic Circuits, and Vol. 7, No. 2, pp. 112-121 Iranian Journal of Electrical and Electronic Engineering SCOPUS
2011 Ashwani K. Rana, Narottam Chand and Vinod Kapoor Modeling Gate Current for Nano Scale MOSFET with Different Gate Spacer, Vol. 20, No. 8, pp. 1659-1675 Journal of Circuits, Systems, and Computers SCIE
2012 Ashwani K. Rana, Narottam Chand and Vinod Kapoor Gate Current Modeling Through High-K Gate Stack MOSFET for VLSI Logic Circuit Analysis, Vol. 9, Issue 1, pp. 43-54 Australian Journal of Electrical & Electronics Engineering SCOPUS
2011 Ashwani K. Rana, Narottam Chand and Vinod Kapoor An Optimal Design of High-K Based MOSFET for Reducing Gate Leakage in VLSI Logic Circuits, Vol 7, No. 1, pp 182-189 The Mediterranean Journal of Electronics and Communications Web of Science
2011 Neha Sharan and Ashwani K. Rana Impact of Strain and Channel Thickness on Performance of Biaxial Strained Silicon MOSFETS, Vol. 2, No. 1, pp. 61-71 International Journal of VLSI design & Communication Systems (VLSICS) Web of Science
2011 Neha Sharan and Ashwani K. Rana Performance Evaluation of Strained Channel NMOS in Nano Regime, Vol. 2, No. 1, pp. 53-58 International Journal of Micro and Nano Systems, Web of Science
2011 Neha Sharan and Ashwani K. Rana Analysis of VLSI Circuits Designed with Single and Dual Channel Strained Silicon MOSFETS in Nanoregime, Vol. 1, No. 1 Journal of VLSI Design Tools & Technology Web of Science
2011 Deepesh Ranka and Ashwani K. Rana “ Performance Evaluation of FD-SOI MOSFETS for Different Metal Gate Work Function,), Vol. 2, No.1 International Journal of VLSI design & Communication Systems Web of Science
2011 Deepesh Ranka, Ashwani K. Rana and Rakesh Kumar Yadav Performance Analysis of FD-SOI MOSFET with Different Gate Spacer Dielectric, Vol. 18, No. 5, pp. 22-27 International Journal of Computer Applications Web of Science
2011 Gaurav Saini and Ashwani K. Rana Physical Scaling Limits of FinFET Structure: A Simulation Study, Vol. 2, No. 1, pp. 26-35 International Journal of VLSI design & Communication Systems Web of Science
2012 Vinay K. Yadav and Ashwani K. Rana Impact of channel doping on DG-MOSFET parameter in nano regime-TCAD simulation, Vol.37, No. 11, pp. 36-41 International journal of computer application Web of Science
2013 Naresh Kumar and Ashwani K. Rana Simulative analysis of various parameters on free space optical communication System, Vol. 34, Issue 3, pp. 237–241 Journal of optical Communication Web of Science
2014 Naresh Kumar and Ashwani Kumar Rana Impact of various parameters on the performance of Free Space Optical Communication System, vol. 124, no. 22, pp. 5774–5776 Science Direct – Optik - International Journal for Light and Electron Optics SCI
2014 Amita Nandal, T. Vigneswaran, and Ashwani Rana DA based efficient testable FIR filter implementation on FPGA using reversible logic, Vol. 33, No. 3, pp.863-884 Circuits, Systems & Signal Processing, Springer SCI
2014 Amita Nandal, T. Vigneswaran, and Ashwani K. Rana Booth multiplier using reversible logic with low power and reduced logical complexity, Vol 7, No. 4, pp. 525–529 Indian Journal of Science and technology SCOPUS
2015 Amita Nandal, T. Vigneswaran and Ashwani K. Rana An Efficient 256-Tap Parallel FIR Digital Filter Implementation Using Distributed Arithmetic Architecture, vol. 54, pp. 605-611 Procedia Computer Science Journal, Elsevier SCOPUS
2014 B.H.V Shrikant and Ashwani K. Rana Performance analysis of Fully Depleted Dual Material (DMG) SOI MOSFET at 25 nm Technology, vol. 3, no. 7 International Journal of Research in Engineering and Technology Web of Science
2013 Amita Nandal, T. Vigneswaran and Ashwani K. Rana An efficient Design of Full Adder using Testable Reversible Gate, Vol. 20, No. 5 WULFENIA Journal SCIE
2013 Amita Nandal, T. Vigneswaran and Ashwani K. Rana Optimized Reversible Logic Based Add and Shift Multiplier using Linear Transformation, Vol. 5, No. 5, pp. 431-435 Advanced Science, Engineering and Medicine SCOPUS
2016 Ashwani K. Rana Device Circuit Co-design to Reduce Gate Leakage Current in VLSI Logic Circuits in Nano Regime, Vol. 29, no.3, pp. 487-500 International Journal of Numerical Modelling: Electronic Networks, Devices and Fields SCI
2016 Rajneesh Sharma and Ashwani K. Rana Scalability Projection of Underlap Fully Depleted Strained Ultra Thin Body Silicon-on-Insulator MOSFETs Using Quantum Potential Simulations, Vol. 11, no. 4, pp. 472-476 Journal of Nanoelectronics and Optoelectronics SCIE
2009 Ashwani K. Rana, Anjna Kumari, Vaishnav Kiran and Sanjay Jamwal Implication of Nanotechnology application on Environment, Vol 50, Issue 1, pp 25-36 IETE Journal of Education Web of Science
2016 Rajneesh Sharma and Ashwani K. Rana Analytical modelling of threshold voltage for underlap Fully Depleted Silicon-On-Insulator MOSFET, Vol. 104, no. 2, pp. 286-296 International Journal of Electronics SCI
2017 Rajneesh Sharma, Rituraj Singh Rathore and Ashwani K. Rana Nanoscale Static Random Access-Memory Design Using Strained Underlap Ultra Thin Silicon on Insulator MOSFET for Improved Performance, Vol. 12, no. 4 pp. 359-364 Journal of Nanoelectronics and Optoelectronics SCIE
2018 Rajneesh Sharma and Ashwani K. Rana Impact of high-k spacer on device performance of nanoscale underlap fully depleted SOI MOSFET,Vol. 27, no. 4 Journal of Circuits, Systems, and Computers SCIE
2017 R. S. Rathore and Ashwani K. Rana Threshold voltage variability induced by spacer-and resist-defined patterning techniques in nanoscale FinFETs, , vol. 16, no. 1, p.013503 Journal of Micro/Nanolithography, MEMS, and MOEMS SCOPUS
2007 R. S. Rathore and Ashwani K. Rana Line edge roughness induced threshold voltage variability in nano-scale FinFETs, vol. 103, pp. 304-313 Superlattices and Microstructures SCI
2017 R. S. Rathore and Ashwani K. Rana Investigation of metal-gate work function variability in FinFET structures and implications for SRAM cell design, vol. 110, pp. 68-81 Superlattices and Microstructures SCI
2017 R. S. Rathore and Ashwani K. Rana Impact of line edge roughness on the performance of 14nm FinFET structure: Device-Circuit Co-design, vol. 113, pp. 213-227 Superlattices and Microstructures SCI
2018 R. S. Rathore and Ashwani K. Rana Device- and circuit-level variability due to random discrete dopant in resist- and spacer-defined nanoscale FinFETs, vol. 17, no. 1, p. 013507 ournal of Micro/Nanolithography, MEMS, and MOEMS SCOPUS
2021 Rajneesh Sharma, Ashwani K Rana, S Kaushal, J B King, A Raman Analysis of Underlap Strained Silicon on Insulator MOSFET for Accurate and Compact Modeling, March 2021 Silicon, Springer SCIE
2018 Shalu Kaundal, Ashwani K. Rana Design and structural optimization of Junctionless FinFET with Gaussian-doped channel,vol. 17, no. 2, pp. 637-645 Journal of Computational Electronics SCIE
2018 Shalu Kaundal, Ashwani K. Rana Evaluation of statistical variability and parametric sensitivity of non-uniformly doped junctionless FinFET, vol. 91, pp. 298-305 Microelectronics reliability SCI
2018 Shalu Kaundal, Ashwani K. Rana Physical Insights on Scaling of Gaussian Channel Design Junctionless FinFET, vol. 13, no. 5, pp. 653-660 Journal of Nanoelectronics and Optoelectronics SCIE
2019 Shalu Kaundal, Ashwani K. Rana Threshold voltage modeling for a Gaussian doped junctionless FinFET, , vol. 18, pp. 1-8 Journal of Computational Electronics SCIE
2019 Shalu Kaundal, Ashwani K. Rana A review of Junctionless Transistor Technology and its Challenges, , vol. 14, no. 3, pp. 310-320 Journal of Nano electronics and Optoelectronics SCIE
2021 Shalu Kaundal, Ashwani K. Rana Impact of Gaussian Doping on SRAM Cell Stability in 14nm Junctionless FinFET Technology. march 2021 Silicon, Springer SCIE
2021 Shelja Kaushal, Ashwani K. Rana and Rajneesh Sharma Performance Evaluation of Negative Capacitance Junctionless FinFET under Extreme Length Scaling, vol. 13, no 10, pp. 3681-3690 Silicon, Springer SCIE
2021 Shelja Kaushal and Ashwani K. Rana Negative Capacitance Junctionless FinFET for Low Power Applications: An Innovative Approach, March 2021 Silicon, Springer SCIE
2021 Shelja Kaushal and Ashwani K. Rana Analytical modelling and simulation of negative capacitance Junctionless FinFET considering fringing field effects, vol. 155, p. 106929 Superlattices and Microstructures, SCI
2022 Shelja Kaushal and Ashwani K. Rana Analytical Model of Sub threshold Drain Current for Nanoscale Negative Capacitance Junctionless FinFET, vol. 121, p. 105382 Microelectronics Journal SCI

Conference Publications



Year Author(s) Title Conference name with place Indexing (SCI/Web of science/Scopus)

Research Projects



Role Project Type Title Funding Agency From To Amount Status Co-Investigator Sanction Order Sanction Date
CO-PI Research and development SMDP-II MeitTY GoI 08/11/2005 31/03/2013 50.00 Lacs Completed Prof Rajeevan Chandel 21(17)2005-VCND 08/11/2005
PI Research and development SMDP-C2SD MeitTY GoI 25/12/2014 30/11/2021 94.09 lacs Completed Prof Rajeevan Chandel 9(1)/2014-MDD 25/12/2014
CO-PI Resource Development ISEA MeitTY GoI 13/05/2014 30/11/2022 36.06 lacs Ongoing Dr narottam Chand 1(2)/2012-ISEA (Vol.11) 19/03/2014
PI National Scheme on Entrepreneurship Development-sponsored Project Pradhan Mantri YUVA Entrepreneurship Ministry of skill development and Entrepreneurship 24/05/2017 31/05/2020 12 lacs Completed Dr Bharat Bhushan Sharma 2017(18)/PMYY/NAT-HUB 01/01/2017
PI Research and development Study and Development of Smart e-System for Crop Protection from Monkeys Himachal Pradesh Council for Science, Technology and Environment 08/01/2018 08/01/2020 7.00 lacs Completed Prof Rajeevan Chandel and Dr Pamita Awasthi SCSTE/F(8)-1/2016-Vol-III/5181-5182 08/01/2018

Research Supervision



Programme Name Scholar Name Research Topic Status Year Co-Suprivisor(s)
Ph.D Dr. (Mrs) Amita Nandal Low Power and High Speed Design of Low Pass Finite Impulse Response Filter using Reversible logic Awarded 2008 NA
Ph.D Dr Rajnish Sharma Analysis of Underlap Fully Depleted Strained SOI MOSFET Awarded 2017 NA
Ph.D Dr Rituraj Singh Rathore Variability Analysis of Nanoscale FinFET Awarded 2018 NA
Ph.D Er Vinod Sharma Thermal Aware FiNFET Design Ongoing 2019 NA
Ph.D Ms Shalu Analysis of graded channel Junctionless MOSFET for low power application Awarded 2019 NA
Ph.D Ms Shelja Kaushal Modeling and Analysis of Negative Capacitance Junctionless FinFET for Low Power SRAM Applications Awarded 2022 NA

Patents



Title Reg./Ref.No. Date of Award/Filling Awarding Agencies Status

Teaching Experience



Position Held Department and Organization From To Total Experience
Assistant Professor (AGP- Rs 6000) ECE, NIT Hamirpur (H.P) 22/08/2000 14/07/2006 6 Years
Assistant Professor (AGP- Rs 7000) ECE, NIT Hamirpur (H.P) 14/07/2006 14/07/2011 5 Years
Assistant Professor (AGP- Rs 8000) ECE, NIT Hamirpur (H.P) 14/07/2011 14/07/2014 3 Years
Associate Professor (AGP- Rs 9000) ECE, NIT Hamirpur (H.P) 14/07/2014 14/07/2018 8 Years

Administrative Experience



Position Held Department and Organization From To
Warden Mega Hostel, NIT Hamirpur 24/06/2013 12/06/2014
Chairman Senate U G Committee (SUGC) Dean Academic, NIT Hamirpur 07/01/2014 06/01/2016
Chairman Senate PG Committee (SPGC) Dean Academic, NIT Hamirpur 06/01/2016 29/09/2016
Faculty In-charge Admission(UG) Dean Academic, NIT Hamirpur 04/04/2014 04/04/2016
Faculty In-charge Admission (PG) Dean Academic, NIT Hamirpur 04/01/2016 05/09/2016
Associate Dean (Electrical Infrastructure & Maintenance) Dean (P&D) NIT Hamirpur 19/01/2022

Book/Chapters Written



Type Title Publisher Author(s) ISBN/ISSN No. Year
Reference Book High Performance Electronic Circuits for VLSI Application Lambert Academic Publishing Co., Germany Dr Ashwani K, Rana 978-3-659-41114-4 2013
Reference Book Analysis of Strained Silicon MOSFET Lambert Academic Publishing Co., Germany Dr Ashwani K. Rana and Dr Neha Sharan 978-3-659-35608-7 2013

Expert Talks



Title Place Year Description of Event
Micro fabrication Techniques adopted in VLSI ECED, Rayat Institute of Engineering and Information Technology, Ropar, Pb 2006 Key note in Latest trends in Telecommunication (LTTC-06)
Material Aspect of High Performance Interconnect in VLSI Circuits ECED, NIT Hamirpur 2006 STC, VLSI design and optimization techniques(VDOT-2006)
Nanoscale Devices ECED, NIT Hamirpur 2006 STC, VLSI Design and recent trends in nano electronics (VDNE-2006)
Marching towards Nanoelectronics ECED, NIT Hamirpur 2006 STC, VLSI Design and recent trends in nano electronics (VDNE-2006)
Design aspect of High Performance Interconnect in VLSI Circuits ECED, NIT Hamirpur 2006 STC, VLSI design and optimization techniques(VDOT-2006)
Digital Modulation Technique ECED, NIT Hamirpur 2008 Seminar on working & application of electronic systems
Nanotechnology-safety Aspect MED, NIT Hamirpur 2008 STC, Mechatronics and Robotics
Nano Device Fundamentals MED, NIT Hamirpur 2008 STC, Mechatronics and Robotics
Impact of nanotechnology on environment ECED, NIT Hamirpur STC, Research Issues in Modern VLSI Devices (RIMVD-09)

Consultancy



Title of Consultancy Client Organization Faculty Involved Amount(INR) Status

International and National Exposure



Sr.No. Title Description

Conferences/Courses Organized



Category Type Title Venue From To Designation
fdp For Faculty VLSI Design & Recent Trends in Nano-Electronics NIT Hamirpur 18/12/2006 22/12/2006 Coordinator
workshop For Faculty Advances in Optical fiber and wireless communications NIT Hamirpur 05/12/2008 06/12/2008 Coordinator
workshop For Faculty Research Issues in Modern VLSI Devices (RIMVD-09) NIT Hamirpur 06/11/2009 07/11/2009 Coordinator
fdp For Faculty Developments in VLSI Devices and Technology (DiVDAT-13) NIT Hamirpur 24/06/2013 28/06/2013 Coordinator
fdp For Faculty Design trends with EDA tools in VLSI, Electronics and Communication (DTEDA-13) NIT Hamirpur 06/07/2013 10/07/2013 Coordinator
fdp For Faculty Analog System Design with ASLKv2010 kit (ASD-14) in association with TI & Edgate Technology P Ltd NIT Hamirpur 22/02/2014 23/02/2014 Coordinator
fdp For Faculty VLSI and Communication System Design with EDA Tools (VCEDA-14) NIT Hamirpur 16/06/2014 20/06/2014 Coordinator
fdp For Faculty EDA Tools and Design Methodologies in VLSI & Communication Systems (ETVCS-15) NIT Hamirpur 12/06/2015 16/06/2015 Coordinator
fdp For Faculty Security Trends in Mobile Ad hoc and sensor Systems (STMASS-16) NIT Hamirpur 11/03/2016 16/03/2016 Coordinator
fdp For Faculty Security Trends in Mobile Ad hoc and sensor Systems (STMASS-17) NIT Hamirpur 02/02/2017 06/02/2017 Coordinator
fdp For Faculty Security Trends in Mobile Ad hoc and sensor Systems (STMASS-18) NIT Hamirpur 15/03/2018 20/03/2018 Coordinator
fdp For Faculty EDA Tools for Electronics System Design (ETESD-18) NIT Hamirpur 01/01/2018 06/01/2018 Coordinator

Profile Summary

Last Update: 14/02/2022 08:21pm
Logo
Name : Dr. Ashwani Kumar Rana
Designation : Associate Professor
Department : Electronics & Communication Engineering
Qualification : B.Tech(NIT H) , M.Tech(IIT Roorkee) , Ph.D (NIT H)
Phone : 254638
Email ID : ashwani@nith.ac.in
Profile URL : https://portfolios.nith.ac.in/index.php?/nith/dr-ashwani-rana-
Date of Birth : 05/23/1974
Date of Joining : 08/22/2000

Specialization

Low Power VLSI, Device Modeling

Education Qualification


Name of the Degree Year of Passing Institute/University
B.Tech (Electronics and Communication Engineering) 1998 NIT Hamirpur (H.P.)
M.Tech. (VLSI Design, Nano Device Modeling) 2006 IIT Roorkee (U.K.)
Ph.D ( VLSI Device Modeling) 2011 NIT Hamirpur (H.P.)

Teaching Experience


Programme Name Department And Organization From To Total Experience
Assistant Professor (AGP- Rs 6000) ECE, NIT Hamirpur (H.P) 22/08/2000 14/07/2006 6 Years
Assistant Professor (AGP- Rs 7000) ECE, NIT Hamirpur (H.P) 14/07/2006 14/07/2011 5 Years
Assistant Professor (AGP- Rs 8000) ECE, NIT Hamirpur (H.P) 14/07/2011 14/07/2014 3 Years
Associate Professor (AGP- Rs 9000) ECE, NIT Hamirpur (H.P) 14/07/2014 14/07/2018 8 Years

Administrative Experience


Position Held Department And Organization From To
Warden Mega Hostel, NIT Hamirpur 24/06/2013 12/06/2014
Chairman Senate U G Committee (SUGC) Dean Academic, NIT Hamirpur 07/01/2014 06/01/2016
Chairman Senate PG Committee (SPGC) Dean Academic, NIT Hamirpur 06/01/2016 29/09/2016
Faculty In-charge Admission(UG) Dean Academic, NIT Hamirpur 04/04/2014 04/04/2016
Faculty In-charge Admission (PG) Dean Academic, NIT Hamirpur 04/01/2016 05/09/2016
Associate Dean (Electrical Infrastructure & Maintenance) Dean (P&D) NIT Hamirpur 19/01/2022

Research Experience

Research Interests : Low Power VLSI Design, Nano Device Modeling, Sensor
Brief Research Statement : 1. To create a research base for the academic development of the students as well as concomitant growth of the students. 2. To expose students to industry to understand the dynamics of industry in term of research challenges. 3. To complete the research/ sponsored projects undertaken. 4. Periodical mentoring of students for a purposeful relationship and mutual research growth. 1. To exposing myself to a variety of things (academic and research) so as to achieve a career which is both rewarding and satisfying. 2. To create world class state-of-the-art facilities and ambience in the department. 3. To develop sensitivity as responsible citizen by introducing research progammes for the development of community.

Research Projects


Role Project Type Title Funding Agency From To Amount Status Co-Investigator Sanction OrderSanction Date
CO-PI Research and development SMDP-II MeitTY GoI 08/11/2005 31/03/2013 50.00 Lacs Completed Prof Rajeevan Chandel 21(17)2005-VCND 08/11/2005
PI Research and development SMDP-C2SD MeitTY GoI 25/12/2014 30/11/2021 94.09 lacs Completed Prof Rajeevan Chandel 9(1)/2014-MDD 25/12/2014
CO-PI Resource Development ISEA MeitTY GoI 13/05/2014 30/11/2022 36.06 lacs Ongoing Dr narottam Chand 1(2)/2012-ISEA (Vol.11) 19/03/2014
PI National Scheme on Entrepreneurship Development-sponsored Project Pradhan Mantri YUVA Entrepreneurship Ministry of skill development and Entrepreneurship 24/05/2017 31/05/2020 12 lacs Completed Dr Bharat Bhushan Sharma 2017(18)/PMYY/NAT-HUB 01/01/2017
PI Research and development Study and Development of Smart e-System for Crop Protection from Monkeys Himachal Pradesh Council for Science, Technology and Environment 08/01/2018 08/01/2020 7.00 lacs Completed Prof Rajeevan Chandel and Dr Pamita Awasthi SCSTE/F(8)-1/2016-Vol-III/5181-5182 08/01/2018

Journal Publications


Year Author(s) Journal Name Title & Vol. No. Indexing (SCI/Web of science/Scopus)
2007 Ashwani K. Rana and S.Dasgupta Journal of Computational and Theoretical Nanoscience (CTN) Unified Compact Modeling of a gate Tunneling Current considering Image Force Induced Barrier Lowering for a nanoscale N-MOSFET and Vol. 4, No. 3, pp. 482-487 SCOPUS
2007 Ashwani K. Rana and S.Dasgupta Journal of Computational and Theoretical Nanoscience (CTN) Analytic Modeling of Non-Uniform Graded Dopant Profile of Polysilicon Gate in Gate Tunneling Current for N-MOSFET in Nanoscale Regime and Vol. 4, No. 1, pp. 179-185 SCOPUS
2008 Ashwani K. Rana and S.Dasgupta Journal of Computational and Theoretical Nanoscience (CTN), Gate Leakage Power analysis for a Nanoscale N-MOSFET and Vol. 5, No. 11, pp. 2180-2185 SCOPUS
2009 Ashwani K. Rana, Shashi B. Rana Anjna Kumari, Vaishnav Kiran International Journal of Recent trends in Engineering Significance of Nanotechnology in construction Engineering and Vol. 1, No. 4, pp. 46-48 Web of Science
2009 Ashwani K. Rana, Narottam Chand and Vinod Kapoor International Journal of Electrical and Electronics Engineering Trap Assisted Tunneling Model for Gate Current in Nano Scale MOSFET with High-K Gate Dielectrics and Vol. 3, No. 7, pp. 402-409 Web of Science
2009 Ashwani K. Rana, Narottam Chand and Vinod Kapoor International Journal of Electrical and Electronics Engineering Gate Tunnel Current Calculation for N-MOSFET Based on Deep Sub-Micron Effects and Vol. 3, No. 7, pp. 426-434 Web of Science
2010 Ashwani K. Rana, Narottam Chand and Vinod Kapoor Journal of Electrical and Electronics Engineering Analytical Gate Current Modeling in Nano Scale MOSFET with High-k Gate Stack Structure and Vol. 3, No. 2, pp. 169-174 Web of Science
2010 Ashwani K. Rana, Narottam Chand and Vinod Kapoor International Journal of Micro-Nano Scale Transport Gate Current Modeling and Optimization of High-k Gate Stack MOSFET Structure in Nano Scale Regime and Vol. 1, No. 3, pp. 253-267 Web of Science
2010 Ashwani K. Rana, Narottam Chand and Vinod Kapoor Journal of Nanoelectronics and Optoelectronics Impact of Gate Engineering on Gate Leakage Behavior of Nano Scale MOSFETs with High-k Dielectrics and Vol. 5, No. 3, pp. 343-348 SCIE
2010 Ashwani K. Rana, Narottam Chand and Vinod Kapoor Journal of Nanoengineering and Nanosystems Gate Leakage Reduction through the use of Source/Drain-to-Gate Non-overlapped MOSFET Structure and Vol. 224, No. 4, pp. 173-181 Web of Science
2011 Ashwani K. Rana, Narottam Chand and Vinod Kapoor Journal of Engineering and Applied Science Analysis and Application of Hybrid MOSFET Structure for Low Gate Leakage,” Journal of Engineering and Applied Science, Vol. 6, No. 1, pp. 38-46 Web of Science
2011 Ashwani K. Rana, Narottam Chand and Vinod Kapoor Journal of Computational Electronics Gate Leakage Behavior of Source/Drain-to-gate Non-overlapped MOSFET Structure and Vol. 10, No. 1-2, pp. 222-228 SCI
2011 Ashwani K. Rana, Narottam Chand and Vinod Kapoor Journal of Semiconductors Gate Current Modeling and Optimal Design of Nanoscale Non-Overlapped Gate to Source/Drain MOSFET, and Vol. 32, No. 7, pp. 074001-6 SCIE
2011 Ashwani K. Rana, Narottam Chand and Vinod Kapoor Multidiscipline Modeling in Materials and Structures Modeling Gate Current of Nano Scale MOSFET for Circuit Simulation and Vol. 7, No. 2, pp. 115-130 SCOPUS
2011 Ashwani K. Rana, Narottam Chand and Vinod Kapoor Iranian Journal of Electrical and Electronic Engineering Gate Leakage Aware Optimal Design of Modified Hybrid Nanoscale MOSFET and Its Application to Logic Circuits, and Vol. 7, No. 2, pp. 112-121 SCOPUS
2011 Ashwani K. Rana, Narottam Chand and Vinod Kapoor Journal of Circuits, Systems, and Computers Modeling Gate Current for Nano Scale MOSFET with Different Gate Spacer, Vol. 20, No. 8, pp. 1659-1675 SCIE
2012 Ashwani K. Rana, Narottam Chand and Vinod Kapoor Australian Journal of Electrical & Electronics Engineering Gate Current Modeling Through High-K Gate Stack MOSFET for VLSI Logic Circuit Analysis, Vol. 9, Issue 1, pp. 43-54 SCOPUS
2011 Ashwani K. Rana, Narottam Chand and Vinod Kapoor The Mediterranean Journal of Electronics and Communications An Optimal Design of High-K Based MOSFET for Reducing Gate Leakage in VLSI Logic Circuits, Vol 7, No. 1, pp 182-189 Web of Science
2011 Neha Sharan and Ashwani K. Rana International Journal of VLSI design & Communication Systems (VLSICS) Impact of Strain and Channel Thickness on Performance of Biaxial Strained Silicon MOSFETS, Vol. 2, No. 1, pp. 61-71 Web of Science
2011 Neha Sharan and Ashwani K. Rana International Journal of Micro and Nano Systems, Performance Evaluation of Strained Channel NMOS in Nano Regime, Vol. 2, No. 1, pp. 53-58 Web of Science
2011 Neha Sharan and Ashwani K. Rana Journal of VLSI Design Tools & Technology Analysis of VLSI Circuits Designed with Single and Dual Channel Strained Silicon MOSFETS in Nanoregime, Vol. 1, No. 1 Web of Science
2011 Deepesh Ranka and Ashwani K. Rana International Journal of VLSI design & Communication Systems “ Performance Evaluation of FD-SOI MOSFETS for Different Metal Gate Work Function,), Vol. 2, No.1 Web of Science
2011 Deepesh Ranka, Ashwani K. Rana and Rakesh Kumar Yadav International Journal of Computer Applications Performance Analysis of FD-SOI MOSFET with Different Gate Spacer Dielectric, Vol. 18, No. 5, pp. 22-27 Web of Science
2011 Gaurav Saini and Ashwani K. Rana International Journal of VLSI design & Communication Systems Physical Scaling Limits of FinFET Structure: A Simulation Study, Vol. 2, No. 1, pp. 26-35 Web of Science
2012 Vinay K. Yadav and Ashwani K. Rana International journal of computer application Impact of channel doping on DG-MOSFET parameter in nano regime-TCAD simulation, Vol.37, No. 11, pp. 36-41 Web of Science
2013 Naresh Kumar and Ashwani K. Rana Journal of optical Communication Simulative analysis of various parameters on free space optical communication System, Vol. 34, Issue 3, pp. 237–241 Web of Science
2014 Naresh Kumar and Ashwani Kumar Rana Science Direct – Optik - International Journal for Light and Electron Optics Impact of various parameters on the performance of Free Space Optical Communication System, vol. 124, no. 22, pp. 5774–5776 SCI
2014 Amita Nandal, T. Vigneswaran, and Ashwani Rana Circuits, Systems & Signal Processing, Springer DA based efficient testable FIR filter implementation on FPGA using reversible logic, Vol. 33, No. 3, pp.863-884 SCI
2014 Amita Nandal, T. Vigneswaran, and Ashwani K. Rana Indian Journal of Science and technology Booth multiplier using reversible logic with low power and reduced logical complexity, Vol 7, No. 4, pp. 525–529 SCOPUS
2015 Amita Nandal, T. Vigneswaran and Ashwani K. Rana Procedia Computer Science Journal, Elsevier An Efficient 256-Tap Parallel FIR Digital Filter Implementation Using Distributed Arithmetic Architecture, vol. 54, pp. 605-611 SCOPUS
2014 B.H.V Shrikant and Ashwani K. Rana International Journal of Research in Engineering and Technology Performance analysis of Fully Depleted Dual Material (DMG) SOI MOSFET at 25 nm Technology, vol. 3, no. 7 Web of Science
2013 Amita Nandal, T. Vigneswaran and Ashwani K. Rana WULFENIA Journal An efficient Design of Full Adder using Testable Reversible Gate, Vol. 20, No. 5 SCIE
2013 Amita Nandal, T. Vigneswaran and Ashwani K. Rana Advanced Science, Engineering and Medicine Optimized Reversible Logic Based Add and Shift Multiplier using Linear Transformation, Vol. 5, No. 5, pp. 431-435 SCOPUS
2016 Ashwani K. Rana International Journal of Numerical Modelling: Electronic Networks, Devices and Fields Device Circuit Co-design to Reduce Gate Leakage Current in VLSI Logic Circuits in Nano Regime, Vol. 29, no.3, pp. 487-500 SCI
2016 Rajneesh Sharma and Ashwani K. Rana Journal of Nanoelectronics and Optoelectronics Scalability Projection of Underlap Fully Depleted Strained Ultra Thin Body Silicon-on-Insulator MOSFETs Using Quantum Potential Simulations, Vol. 11, no. 4, pp. 472-476 SCIE
2009 Ashwani K. Rana, Anjna Kumari, Vaishnav Kiran and Sanjay Jamwal IETE Journal of Education Implication of Nanotechnology application on Environment, Vol 50, Issue 1, pp 25-36 Web of Science
2016 Rajneesh Sharma and Ashwani K. Rana International Journal of Electronics Analytical modelling of threshold voltage for underlap Fully Depleted Silicon-On-Insulator MOSFET, Vol. 104, no. 2, pp. 286-296 SCI
2017 Rajneesh Sharma, Rituraj Singh Rathore and Ashwani K. Rana Journal of Nanoelectronics and Optoelectronics Nanoscale Static Random Access-Memory Design Using Strained Underlap Ultra Thin Silicon on Insulator MOSFET for Improved Performance, Vol. 12, no. 4 pp. 359-364 SCIE
2018 Rajneesh Sharma and Ashwani K. Rana Journal of Circuits, Systems, and Computers Impact of high-k spacer on device performance of nanoscale underlap fully depleted SOI MOSFET,Vol. 27, no. 4 SCIE
2017 R. S. Rathore and Ashwani K. Rana Journal of Micro/Nanolithography, MEMS, and MOEMS Threshold voltage variability induced by spacer-and resist-defined patterning techniques in nanoscale FinFETs, , vol. 16, no. 1, p.013503 SCOPUS
2007 R. S. Rathore and Ashwani K. Rana Superlattices and Microstructures Line edge roughness induced threshold voltage variability in nano-scale FinFETs, vol. 103, pp. 304-313 SCI
2017 R. S. Rathore and Ashwani K. Rana Superlattices and Microstructures Investigation of metal-gate work function variability in FinFET structures and implications for SRAM cell design, vol. 110, pp. 68-81 SCI
2017 R. S. Rathore and Ashwani K. Rana Superlattices and Microstructures Impact of line edge roughness on the performance of 14nm FinFET structure: Device-Circuit Co-design, vol. 113, pp. 213-227 SCI
2018 R. S. Rathore and Ashwani K. Rana ournal of Micro/Nanolithography, MEMS, and MOEMS Device- and circuit-level variability due to random discrete dopant in resist- and spacer-defined nanoscale FinFETs, vol. 17, no. 1, p. 013507 SCOPUS
2021 Rajneesh Sharma, Ashwani K Rana, S Kaushal, J B King, A Raman Silicon, Springer Analysis of Underlap Strained Silicon on Insulator MOSFET for Accurate and Compact Modeling, March 2021 SCIE
2018 Shalu Kaundal, Ashwani K. Rana Journal of Computational Electronics Design and structural optimization of Junctionless FinFET with Gaussian-doped channel,vol. 17, no. 2, pp. 637-645 SCIE
2018 Shalu Kaundal, Ashwani K. Rana Microelectronics reliability Evaluation of statistical variability and parametric sensitivity of non-uniformly doped junctionless FinFET, vol. 91, pp. 298-305 SCI
2018 Shalu Kaundal, Ashwani K. Rana Journal of Nanoelectronics and Optoelectronics Physical Insights on Scaling of Gaussian Channel Design Junctionless FinFET, vol. 13, no. 5, pp. 653-660 SCIE
2019 Shalu Kaundal, Ashwani K. Rana Journal of Computational Electronics Threshold voltage modeling for a Gaussian doped junctionless FinFET, , vol. 18, pp. 1-8 SCIE
2019 Shalu Kaundal, Ashwani K. Rana Journal of Nano electronics and Optoelectronics A review of Junctionless Transistor Technology and its Challenges, , vol. 14, no. 3, pp. 310-320 SCIE
2021 Shalu Kaundal, Ashwani K. Rana Silicon, Springer Impact of Gaussian Doping on SRAM Cell Stability in 14nm Junctionless FinFET Technology. march 2021 SCIE
2021 Shelja Kaushal, Ashwani K. Rana and Rajneesh Sharma Silicon, Springer Performance Evaluation of Negative Capacitance Junctionless FinFET under Extreme Length Scaling, vol. 13, no 10, pp. 3681-3690 SCIE
2021 Shelja Kaushal and Ashwani K. Rana Silicon, Springer Negative Capacitance Junctionless FinFET for Low Power Applications: An Innovative Approach, March 2021 SCIE
2021 Shelja Kaushal and Ashwani K. Rana Superlattices and Microstructures, Analytical modelling and simulation of negative capacitance Junctionless FinFET considering fringing field effects, vol. 155, p. 106929 SCI
2022 Shelja Kaushal and Ashwani K. Rana Microelectronics Journal Analytical Model of Sub threshold Drain Current for Nanoscale Negative Capacitance Junctionless FinFET, vol. 121, p. 105382 SCI

Conference Publications


Year Author(s) Conference Title Indexing

Book/Chapters Written


Type (Book/Chapter) Author(s) Title Publisher ISBN/ISSN No. Year
Reference Book Dr Ashwani K, Rana High Performance Electronic Circuits for VLSI Application Lambert Academic Publishing Co., Germany 978-3-659-41114-4 2013
Reference Book Dr Ashwani K. Rana and Dr Neha Sharan Analysis of Strained Silicon MOSFET Lambert Academic Publishing Co., Germany 978-3-659-35608-7 2013

Research Supersion


Programme Name Scholar Name Research Topic Status Year Co-Superivisor(s)
Ph.D Dr. (Mrs) Amita Nandal Low Power and High Speed Design of Low Pass Finite Impulse Response Filter using Reversible logic Awarded 2008 NA
Ph.D Dr Rajnish Sharma Analysis of Underlap Fully Depleted Strained SOI MOSFET Awarded 2017 NA
Ph.D Dr Rituraj Singh Rathore Variability Analysis of Nanoscale FinFET Awarded 2018 NA
Ph.D Er Vinod Sharma Thermal Aware FiNFET Design Ongoing 2019 NA
Ph.D Ms Shalu Analysis of graded channel Junctionless MOSFET for low power application Awarded 2019 NA
Ph.D Ms Shelja Kaushal Modeling and Analysis of Negative Capacitance Junctionless FinFET for Low Power SRAM Applications Awarded 2022 NA

Patents


Name Reg./Ref.No. Date of Award/Filling Awarding Agencies Status

Conferences/Workshop/Courses Organized


Category Type Title Venue From To Designation
fdp For Faculty VLSI Design & Recent Trends in Nano-Electronics NIT Hamirpur 18/12/2006 22/12/2006 Coordinator
workshop For Faculty Advances in Optical fiber and wireless communications NIT Hamirpur 05/12/2008 06/12/2008 Coordinator
workshop For Faculty Research Issues in Modern VLSI Devices (RIMVD-09) NIT Hamirpur 06/11/2009 07/11/2009 Coordinator
fdp For Faculty Developments in VLSI Devices and Technology (DiVDAT-13) NIT Hamirpur 24/06/2013 28/06/2013 Coordinator
fdp For Faculty Design trends with EDA tools in VLSI, Electronics and Communication (DTEDA-13) NIT Hamirpur 06/07/2013 10/07/2013 Coordinator
fdp For Faculty Analog System Design with ASLKv2010 kit (ASD-14) in association with TI & Edgate Technology P Ltd NIT Hamirpur 22/02/2014 23/02/2014 Coordinator
fdp For Faculty VLSI and Communication System Design with EDA Tools (VCEDA-14) NIT Hamirpur 16/06/2014 20/06/2014 Coordinator
fdp For Faculty EDA Tools and Design Methodologies in VLSI & Communication Systems (ETVCS-15) NIT Hamirpur 12/06/2015 16/06/2015 Coordinator
fdp For Faculty Security Trends in Mobile Ad hoc and sensor Systems (STMASS-16) NIT Hamirpur 11/03/2016 16/03/2016 Coordinator
fdp For Faculty Security Trends in Mobile Ad hoc and sensor Systems (STMASS-17) NIT Hamirpur 02/02/2017 06/02/2017 Coordinator
fdp For Faculty Security Trends in Mobile Ad hoc and sensor Systems (STMASS-18) NIT Hamirpur 15/03/2018 20/03/2018 Coordinator
fdp For Faculty EDA Tools for Electronics System Design (ETESD-18) NIT Hamirpur 01/01/2018 06/01/2018 Coordinator

Expert Talks


Title Place Year Description of Event
Micro fabrication Techniques adopted in VLSI ECED, Rayat Institute of Engineering and Information Technology, Ropar, Pb 2006 Key note in Latest trends in Telecommunication (LTTC-06)
Material Aspect of High Performance Interconnect in VLSI Circuits ECED, NIT Hamirpur 2006 STC, VLSI design and optimization techniques(VDOT-2006)
Nanoscale Devices ECED, NIT Hamirpur 2006 STC, VLSI Design and recent trends in nano electronics (VDNE-2006)
Marching towards Nanoelectronics ECED, NIT Hamirpur 2006 STC, VLSI Design and recent trends in nano electronics (VDNE-2006)
Design aspect of High Performance Interconnect in VLSI Circuits ECED, NIT Hamirpur 2006 STC, VLSI design and optimization techniques(VDOT-2006)
Digital Modulation Technique ECED, NIT Hamirpur 2008 Seminar on working & application of electronic systems
Nanotechnology-safety Aspect MED, NIT Hamirpur 2008 STC, Mechatronics and Robotics
Nano Device Fundamentals MED, NIT Hamirpur 2008 STC, Mechatronics and Robotics
Impact of nanotechnology on environment ECED, NIT Hamirpur STC, Research Issues in Modern VLSI Devices (RIMVD-09)

Consultancy


Title of Consultancy Client Organization Faculty Involved Amount(INR) Status

International and National Exposure


Sr.No. Title Description

Honors & Recognitions Achieved


Sr.No. Title Activity Given By Year