profile
Dr. Dharmendra Singh Yadav
Assistant ProfessorDr. Dharmendra Singh Yadav received Ph.D. degree in VLSI Design Engineering from PDPM Indian Institute of Information Technology, Design and Manufacturing, Jabalpur Madhya Pradesh in April 2018. He received M.E degree in Electronics and Tele Communication from Shri Govindram Seksaria Institute of Technology and Science, Indore Madhya Pradesh in 2011 and B.E degree in Electronics and Communication Engineering from Samrat Ashok Technological Institute Vidisha Madhya Pradesh in 2009. He has qualified National level examination like GATE in Electronics and Communication Engineering. His research interest includes Low-power MOSFETs, Multigate MOSFET, Tunnel FET, Solid-State Devices, Semiconductor Devices: Physics, Simulation and modelling of nanoscale devices for low power and high frequency applications, Circuit level implementation of devices in nanoelectronics, and Nanotechnology based thin film devices for sensing applications also FETs Based Biosensor Strain Analysis, Ferroelectrics Based FETs etc. He is also a peer reviewer and member of several reputed SCI journals/ conferences like IEEE and Scopus.
| Name | : | Dr. Dharmendra Singh Yadav |
| Designation | : | Assistant Professor |
| Department | : | Electronics & Communication Engineering |
| Qualification | : | B.E, M.E, Ph.D. |
| Phone | : | 01972 -254600 |
| Email ID | : | dsyadav@nith.ac.in |
| Google Scholar Link | : | View |
| Vidwan Link | : | View |
| Publons Link | : | View |
| Linkedin/Orcid/Other Link | : | View |
Resume Not Available..
General Information
| Name | : | Dr. Dharmendra Singh Yadav |
| Designation | : | Assistant Professor |
| Department | : | Electronics & Communication Engineering |
| Qualification | : | B.E, M.E, Ph.D. |
| Date of Birth | : | |
| Date of joining | : | 10/12/2018 |
Contact Details
| Phone | : | 01972 -254600 |
| Email ID | : | dsyadav@nith.ac.in |
Specialization
Position Held
| Position | Department Name | Institute Name | Time Period |
|---|
Educational Qualification
| Name of the Degree | Year of Passing | Institute/University |
|---|---|---|
| B.E | 2009 | Samrat Ashok Technological Institute Vidisha M.P |
| M.E | 2011 | Shri Govindram Seksaria Institute of Technology and Science Indore M.P |
| Ph.D. (VLSI Design) | 2018 | PDPM Indian Institute of Information Technology, Design & Manufacturing Jabalpur M.P |
Honors & Recognitions Achieved
| Sr.No. | Title | Activity | Given By | Year |
|---|---|---|---|---|
| 1 | 3D Networking and Collaborative Environment for Online Education | Best Paper Award | 10th International Conference on Emerging Trends in Engineering and Technology - Signal and Information Processing (ICETET-SIP-22) held at G H Raisoni College of Engineering, Nagpur during 29th - 30th April 2022, technically supported by IEEE Bombay Section and Nagpur Sub-Section in association with GHR Lab and Research Center | 2022 |
| 2 | Cloud based psychopathology companion | Best Paper Award | 10th International Conference on Emerging Trends in Engineering and Technology - Signal and Information Processing (ICETET-SIP-22) held at G H Raisoni College of Engineering, Nagpur during 29th - 30th April 2022, technically supported by IEEE Bombay Section and Nagpur Sub-Section in association with GHR Lab and Research Center | 2022 |
Research Experience
| Research Interests : | Tunnel FET, Multigate MOSFET, Solid-State Devices, Semiconductor Devices: Physics, Simulation and modelling of nanoscale devices for low power and high frequency applications, Circuit level implementation of devices in nanoelectronics, Low-power MOSFET and TFETs. | |
| Brief Research Statement : | Requirement of energy efficient transistor which supports for high frequency ultra low power application. Need of smaller off-currents and standby power dissipation. Need of lesser switching delay which improves circuit level performances. Reducing supply voltage (VDD) while keeping leakage current low is one of the major concern for minimizing energy consumption. The thermal limit of MOSFET sub threshold swing (SS) restricts lowering threshold voltage (Vt), causing significant performance degradation at low VDD. Need of scaling in devices with reduced gate leakage. |
Journal Publications
| Year | Author(s) | Title & Vol. No. | Journal Name | Indexing (SCI) Web of Science/Scopus |
|---|---|---|---|---|
| 2018 | D. S. Yadav, D. Sharma, S.Tirkey, D. G. sharma, S. Bajpai, D. Soni, S. Yadav, Mohd. Aslam and N. Sharma | Hetero-material CPTFET with high-frequency and linearity analysis for ultra-low power applications, doi: 10.1049/mnl.2018.5075 Accepted on 11 July. 2018 | IET, Micro Nano Letters | SCI |
| 2018 | D. S. Yadav, A. Verma, D. Sharma, and N. Sharma | Study of Metal Strip Insertion and its Optimization in Doping Less TFET. Vol. no. 122, pp. 577-586, Oct 2018 | Superlattices and Microstructures, Elsevier | SCI |
| 2018 | D. S. Yadav, D. Sharma, S. Tirkey, and V. Bajaj | A systematic investigation for performance improvement by integrated effect of gate under lapping, dual work functionality and hetero gate dielectric for CPTFET vol. 17, Issue. 1, pp 118-128, Mar 2018 | Journal of Computational Electronics, Springer | SCI |
| 2017 | D. S. Yadav, A. Verma, D. Sharma, S. Tirkey, and B.R. Raad | Comparative investigation of novel hetero gate dielectric and drain engineered charge plasma TFET for improved DC and RF performance vol. 111, pp. 123-133, Nov. 2017 | Superlattices and Microstructures, Elsevier | SCI |
| 2017 | D. S. Yadav, D. Sharma, A. Kumar, D. Rathor, R. Agrawal, S. Tirkey, B. R. Raad, and V. Bajaj, | Performance investigation of hetero material (InAs/Si) based charge plasma TFET vol.12, no.6, pp.358–363, Jan. 2017 | IET, Micro Nano Letters | SCI |
| 2016 | D. S. Yadav, B. R. Raad, and D. Sharma | A novel gate and drain engineered charge plasma tunnel field-effect transistor for low sub-threshold swing and ambipolar nature,” vol. no. 100, pp. 266–273, Dec. 2016 | Superlattices and Microstructures, Elsevier | SCI |
| 2016 | D. S. Yadav, D. Sharma, B.R. Raad, V. Bajaj, | “Impactful Study of Dual Work Function, Underlap and Hetero Gate Dielectric on TFET with Different Drain Doping Profile for High Frequency Performance Estimation and Optimization,” vol. no. 96, pp. 36–46, Aug. 2016 | Superlattices and Microstructures, Elsevier | SCI |
| 2018 | S. Tirkey, D. Sharma, B. Raad, D. S. Yadav | A Novel Approach to Improve the Performance of Charge Plasma Tunnel Field Effect Transistor" vol. 65, no.1, pp. 282-289, Jan. 2018. | IEEE Transaction on Electron Devices | SCI |
| 2017 | S. Tirkey, D. Sharma, D. S. Yadav, and S. Yadav | Analysis of a Novel Metal Implant Junctionless Tunnel Field-Effect Transistor for Better DC and Analog/RF Electrostatic Parameters, vol. 63, no.9, pp. 3943-3950, Sep. 2017 | IEEE Transaction on Electron Devices | SCI |
| 2017 | M. Verma, S. Tirkey, S. Yadav, D. Sharma, and D.S. Yadav | Performance Assessment of a Novel Vertical Dielectrically Modulated TFET-Based Biosensor. vol. 63, no. 9, pp. 3841-3848, Sep. 2017 | IEEE Transaction on Electron Devices | SCI |
| 2016 | B. R. Raad, D. Sharma, P. Kondekar, K. Nigam, and D. S. Yadav | Drain work function engineered doping-Less charge plasma TFET for ambipolar suppression and RF performance improvement: A proposal design and investigation", vol. 63, no. 10, pp. 3950-3957, Oct. 2016 | IEEE Transaction on Electron Devices | SCI |
| 2016 | D. Singh, D. Sharma, S. Pandey, K. Nigam, D. S. Yadav and P. N. Kondekar | A Charge Plasma based Dielectric Modulated Junctionless TFET for Biosensor Label Free Detection. vol. 64, no. 1, pp. 271-278, Jan. 2016 | IEEE Transaction on Electron Devices | SCI |
| 2017 | S. Tirkey, B. R. Raad, D. Sharma, and D. S. Yadav | Introduction of a metal strip in oxide region of junctionless tunnel field-effect transistor to improve DC and RF performance,” vol. no. 16, Issue. 3, pp 714- 720 Sep. 2017. | Journal of computational electronics Springer | SCI |
| 2016 | D. Sharma, B. R. Raad, D.S. Yadav, P. Kondekar, and K. Nigam | 2-D Potential, Electric Field and Drain Current Model of Source Pocket Hetero Gate Dielectric Triple Work Function Tunnel Field-Effect Transistor. vol. 12, no. 1, pp. 11-16, Sep. 2016 | IET, Micro Nano Letters | SCI |
| 2018 | A Lemtur, D Sharma, P Suman, J Patel, D S Yadav and N Sharma | Performance analysis of gate all around GaAsP/AlGaSb CPTFET,” vol. no. 117, pp. 364–372, Mar. 2018 | Superlattices and Microstructures, Elsevier | SCI |
| 2018 | S Gupta, D Sharma , D Soni , S Yadav ; M. Aslam , D S Yadav, K Nigam, N Sharma | Examination of the impingement of interface trap charges on heterogeneous gate dielectric dual material control gate tunnel field effect transistor for the refinement of device reliability. Vol. no. 13 , Issue: 8 pp: 1192 - 1196, 2018 | IET, Micro Nano Letters | SCI |
| 2018 | M. Aslam, D Sharma, D Soni, S Yadav , B R Raad , D S Yadav , N Sharma | Effective design technique for improvement of electrostatics behaviour of dopingless TFET: proposal, investigation and optimisation. Year: 2018 , Vol. no. 13 , Issue: 10 pp 1480 - 1485, 2018 | IET, Micro Nano Letters | SCI |
| 2018 | S Tirkey, D S yadav, D Sharma | Controlling ambipolar current of dopingless tunnel field-effect transistor https://doi.org/10.1007/s00339-018-2237-6 | Applied Physics A, Springer | SCI |
| 2019 | D. Soni, A. K. Behra, D.Sharma, D.P.Samajdar, D.S.Yadav | Structural Modification of Doped Tunnel Field Effect Transistor for Enhanced Conduction Current and Lower Subthreshold Swing.Year: 2019 , Vol. no. 14 , Issue: 11 pp 1539-1547, 2019 | Journal of Nanoelectronics and Optoelectronics | SCI |
| 2020 | A. Lodhi, C. Rajan, A.K. Behera, D.P.Samajdar, D. Soni, D. S. Yadav | Sensitivity and sensing speed analysis of extended nano-cavity and source over electrode in Si/SiGe based TFET biosensor | Applied Physics A, Springer | SCI |
| 2021 | A.Dixit, D.P. Samajdar, N. Bagga, D. S. Yadav | Performance investigation of a novel GaAs1-xSbx-on-insulator (GASOI) FinFET: Role of interface trap charges and hetero dielectric | Materials Today Communications Elsevier | SCI |
| 2021 | N. Parmar, P. Singh, D. P. Samajdar, D. S. Yadav | Temperature impact on linearity and analog/RF performance metrics of a novel charge plasma tunnel FET | Applied Physics A, Springer | SCI |
| 2021 | P. Singh, D. S. Yadav | "Impact of temperature on analog/RF, linearity and reliability performance metrics of tunnel FET with ultra‑thin source region" | Applied Physics A, Springer | SCI |
| 2021 | P. Singh, D. S. Yadav | Impactful Study of F-shaped Tunnel FET | Silicon, Springer | SCI |
| 2021 | S. Kumar, D. S. Yadav | Temperature analysis on electrostatics performance parameters of dual metal gate step channel TFET | Applied Physics A, Springer | SCI |
| 2021 | A. K. Behera, C. Rajan, D. P. Samajdar, A. Lodhi, J. Patel, K. Mishra & D. S. Yadav | Performance Analysis of Sigma Delta ADC Developed using Electrically Doped GAPSb/InP Gate All Around Tunnel Field Effect Transistor | Journal of Electronic Materials, Springer | SCI |
| 2021 | P. Singh, D. S. Yadav | Design and Investigation of F-shaped Tunnel FET with Enhanced Analog/RF Parameters | Silicon, Springer | SCI |
| 2021 | M. Kamal, D. S. Yadav | Effects of linearity and reliability analysis for HGO-DW-SCTFET with temperature variation for high frequency application | Silicon, Springer | SCI |
Conference Publications
| Year | Author(s) | Title | Conference name with place | Indexing (SCI/Web of science/Scopus) |
|---|---|---|---|---|
| 2018 | D. S. Yadav, D. Sharma, D. G. Sharma and S. Bajpai | High Frequency Analysis of GaAsP/InSb Hetero Junction Double Gate Tunnel Field Effect Transistor | IEEE’s 3rd International Conference for Convergence in Technology (I2CT), .sponsored by IEEE Bombay Section, held from 6th — 8th April, 2018, at Hotel Gateway (TAJ), Hinjewadi, Pune, Maharashtra , India | SCI / IEEE International |
| 2017 | D. S. Yadav, D. Sharma, S. Tirkey, D. Soni, D. G. Sharma and S. Bajpai | A Comparative Study of GaP/SiGe heterojunction double gate Tunnel Field Effect Transistor | IEEE International Symposium on Nanoelectronics and Information Systems (IEEE iNIS- 2017), held from18th —20th Dec, 2017, at OIST Bhopal, India. | SCI / IEEE International |
| 2017 | D. Soni, D. Sharma, S. Yadav, Mohd. Aslam and D. S. Yadav | Gate metal work function engineering for the improvement of electrostatic behaviour of doped tunnel field effect transistor | IEEE International Symposium on Nanoelectronics and Information Systems (IEEE iNIS-2017), held from 18th—20th Dec, 2017, at OIST Bhopal, India | SCI / IEEE International |
| 2017 | D. S. Yadav, D. Sharma, R. Agrawal, G. Prajapati, S. Tirkey, B. R. Raad, and V. Bajaj | Temperature based performance analysis of doping-less Tunnel Field Effect Transistor | IEEE International Conference on Information Communication Instrumentation and Control (ICICIC -2017), held from 17th -19th Aug, 2017, at Medi-caps University Indore India | SCI / IEEE International |
| 2017 | S. Tirkey, D. S. Yadav, D. Sharma and V. Bajaj | Controlling Ambipolar Behavior and Improving Radio Frequency Performance of Hetero Junction Double Gate TFET by Dual Work-Function, Hetero Gate Dielectric, Gate Underlap: Assessment and Optimization | IEEE International Conference on Information Communication Instrumentation and Control (ICICIC -2017), held from 17th -19th Aug, 2017, at Medi-caps University Indore India. | SCI / IEEE International |
| 2016 | D. S. Yadav, D. Sharma, B. R. Raad and V. Bajaj | Dual Workfunction Hetero Gate Dielectric Tunnel Field-Effect Transistor Performance Analysis | IEEE international conference on advanced communication control and computing technologies (ICACCT 2016) organized by Syed Ammal Engineering College held from 25th -27th May,2016, at Ramanathapuram, Tamilnadu, India | SCI / IEEE International |
| 2020 | N. Parmar ; D. S. Yadav ; S. Kumar ; R. Sharma ; S. Saraswat ; A. Kumar | Performance Analysis of a Novel Dual Metal Strip Charge Plasma Tunnel FET | 2020 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS) held at MANIT Bhopal | SCI / IEEE International |
| 2020 | S. Saraswat ; D. S. Yadav ; S. Kumar ; N. Parmar ; R. Sharma ; A. Kumar | Performance Analysis of TMG FinFETs for Low Power Application with Improved Analog/RF Characteristics | 2020 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS) held at MANIT Bhopal | SCI / IEEE International |
| 2020 | R. Sharma ; D. S. Yadav; S. Kumar ; N. Parmar ; S. Saraswat ; A. Kumar | Novel Perspective Approach to Improve Performance of Nanowire TFET | 2020 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS) held at MANIT Bhopal | SCI / IEEE International |
| 2020 | S. Kumar ; D. S. Yadav ; S. Saraswat ; N. Parmar ; R. Sharma ; A. Kumar | A Novel Step-Channel TFET for Better Subthreshold Swing and Improved Analog/RF Characteristics | 2020 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS) held at MANIT Bhopal | SCI / IEEE International |
| 2021 | P. Singh, D. S. Yadav .et.al | Doping and Dopingless Tunnel Field Effect Transistor | IEEE, 2021 6th International Conference for Convergence in Technology (I2CT), 2021 | SCI / IEEE International |
| 2021 | P. Singh, D. S. Yadav et.al | A Low Power Single Gate L-shaped TFET for High Frequency Application | IEEE, 2021 6th International Conference for Convergence in Technology (I2CT), 2021 | SCI / IEEE International |
| 2021 | M. Kamal, D. S. Yadav | A Comparative Analysis with Impact of Work Function Engineering of Step Channel TFET | Springer, 4th International Conference on Inventive Material Science and Applications (ICIMA- 2021) | SCI / International |
| 2021 | P. K. Pandey, D. S. Yadav | Parametric Inspection of 6T SRAM Cell | IEEE, 5th International Conference on Trends in Electronics and Informatics (ICOEI 2021) | SCI / IEEE International |
| 2021 | R.Sharma, D. S. Yadav | Temperature dependence of Linearity and RF Performance metrics in DMG GaSb-Si Nanowire TFET | International Conference on Communication, Control and Information Sciences (ICCISc), 2021 | SCI / IEEE International |
| 2021 | R. Sharma, D. S. Yadav | Interface Trap Charges and their impact on Linearity and RF Performance metrics for a Heterodielectric Dual Metal Gate GaSb-Si Nanowire TFET | International Conference on Communication, Control and Information Sciences (ICCISc), 2021 | SCI / IEEE International |
| 2021 | S. Saraswat, D. S. Yadav | Impact of Interface Trap Charge on Analog/RF parameters of Novel Heterogeneous Gate Dielectric Tri-Metal Gate FinFET | International Conference on Communication, Control and Information Sciences (ICCISc), 2021 | SCI / IEEE International |
| 2021 | R. M. Gangadari, D. S. Yadav | Extraction and Comparative Inspection of several parameters of 6T, 8T, 10T SRAM | First International Conference on Advances in Computing and Future Communication Technologies (ICACFCT-2021) | SCI / IEEE International |
| 2021 | V. Choudhary, D. S. Yadav | Analyses of Power, Delay and SNM of 6T & 8T SRAM Cells | "5th International Conference on Electronics, Communication and Aerospace Technology (ICECA 2021) " | SCI / IEEE International |
Research Projects
| Role | Project Type | Title | Funding Agency | From | To | Amount | Status | Co-Investigator | Sanction Order | Sanction Date |
|---|
Research Supervision
| Programme Name | Scholar Name | Research Topic | Status | Year | Co-Suprivisor(s) |
|---|---|---|---|---|---|
| M.Tech | Somya Saraswat | Performance Analysis of Tri-Metal Gate (TMG) FinFETs for low power applications | Completed | 2020 | - |
| M.Tech | Nitesh Parmar | Charge Plasma Tunnel FET: Proposal, Design and Investigation | Completed | 2020 | - |
| M.Tech | Sachin Kumar | Impactful Study of TFET for High Frequency Performance Estimation and Optimization | Completed | 2020 | - |
| M.Tech | Ritwik Sharma | Comprehensive Study of Nanowire Tunnel Field Effect Transistor | Completed | 2020 | - |
| M.Tech | Prince Kumar Pandey | Parametric Analysis of Different SRAM Cells and Designing 4x4 Array | Completed | 2021 | - |
| M.Tech | Manshi Kamal | Analysis of Analog/RF and Linearity Performance for Step Channel Tunnel Field Effect Transistor | Completed | 2021 | - |
| M.Tech | Sangeeta Pandey | Design and performance estimation of 12T SRAM cell on CMOS technology with stability analysis | Completed | 2021 | - |
| M.Tech | Ayush Sharma | Investigation of Drain Engineering based CPTFET | Completed | 2022 | - |
| M.Tech | Vibhash Choudhary | Optimization of SRAM Cells with CMOS Technology | Completed | 2022 | - |
| M.Tech | Rakesh Murthy Gangadari | Design and Investigation of CMOS and TFET based SRAM Memory cell for low power application | Completed | 2022 | - |
| M.Tech | Prajwal Roat | Design and assessment of Tunnel FET with various Engineering Techniques | Completed | 2022 | - |
| Ph.D | Prabhat Singh | Design and investigation of Tunnel FET for low power based circuit application | Ongoing | 2019 | - |
Patents
| Title | Reg./Ref.No. | Date of Award/Filling | Awarding Agencies | Status |
|---|
Teaching Experience
| Position Held | Department and Organization | From | To | Total Experience |
|---|---|---|---|---|
| Assistant professor | Electronics and Communication Engineering, NIT Hamirpur, Himachal Pradesh | 10/12/2018 | Till date |
Administrative Experience
| Position Held | Department and Organization | From | To |
|---|---|---|---|
| Assistant Faculty In charge | Central Security Institute, NIT Hamirpur, Himachal Pradesh | 20/12/2018 | 03/08/2020 |
| Assistant Warden | Himadri Boys Hostel, NIT Hamirpur, Himachal Pradesh | 26/03/2019 | 01/06/2020 |
| Assistant Faculty In charge | Sports & Yoga Activities | 10/04/2019 | 03/08/2020 |
| Assistant Warden | Higiri Boys Hostel, NIT Hamirpur, Himachal Pradesh | 01/06/2020 | 03/08/2020 |
| Departmental Faculty Incharge, SPEC Society | E&CED, NIT Hamirpur, Himachal Pradesh | 21/08/2019 | |
| Departmental Faculty Incharge, VLSI and Nano Lab | E&CED, NIT Hamirpur, Himachal Pradesh | 21/08/2019 | 04/03/2020 |
| Departmental Faculty Incharge, Embedded System Lab | E&CED, NIT Hamirpur, Himachal Pradesh | 04/03/2020 |
Book/Chapters Written
| Type | Title | Publisher | Author(s) | ISBN/ISSN No. | Year |
|---|
Expert Talks
| Title | Place | Year | Description of Event |
|---|
Consultancy
| Title of Consultancy | Client Organization | Faculty Involved | Amount(INR) | Status |
|---|
International and National Exposure
| Sr.No. | Title | Description |
|---|
Conferences/Courses Organized
| Category | Type | Title | Venue | From | To | Designation |
|---|---|---|---|---|---|---|
| fdp | National-NKN FDP (Sponsored by E&ICT Academy, IIT Guwahati) | Antenna Trends | National Institute of Technology Hamirpur | 01/07/2019 | 05/07/2019 | Course Coordinator |
| fdp | National-NKN FDP (Sponsored by E&ICT Academy, IIT Roorkee) | VLSI Chip Design Hands on using open source EDA | National Institute of Technology Hamirpur | 08/07/2019 | 12/07/2019 | Course Coordinator |
| stc | National (Sponsored by IRDT Kanpur UP) | Future Aspect of Electronics and Digital Learning | National Institute of Technology Hamirpur | 16/09/2019 | 21/09/2019 | Course Coordinator |
| workshop | National | Design Challenges of IoT with AI & ML Applications | National Institute of Technology Hamirpur | 30/11/2020 | 04/12/2020 | Convener & Coordinator |
| fdp | National (Sponsored by ATAL AICTE) | Internet of Things | National Institute of Technology Hamirpur | 01/06/2021 | 05/06/2021 | Course Coordinator |
| workshop | National | Intelligent Device Computing, Communication and Signal Processing | National Institute of Technology Hamirpur | 10/01/2022 | 14/01/2022 | Course Coordinator |
Profile Summary
Last Update: 21/06/2022 07:11pm
| Name | : | Dr. Dharmendra Singh Yadav |
| Designation | : | Assistant Professor |
| Department | : | Electronics & Communication Engineering |
| Qualification | : | B.E, M.E, Ph.D. |
| Phone | : | 01972 -254600 |
| Email ID | : | dsyadav@nith.ac.in |
| Profile URL | : | https://portfolios.nith.ac.in/index.php?/nith/dr-dharmendra-singh-yadav |
| Date of Birth | : | |
| Date of Joining | : | 10/12/2018 |
Specialization
VLSI Design: Nano-electronics Devices, Thin films transistors, Semiconductor Device and circuits. Device Modeling: MOS Devices Modeling and Numerical simulation analysis of Semiconductor devices Electrical Characterization of semiconductor devices in MHz and THz frequency ranges. Circuit Design: Ultra Low Power SRAM / DRAM / RRAM based Memory Circuit Design from Devices to Array Architecture using CMOS and Advanced CMOS Devices technologies. Machine Learning in Semiconductor device/circuit-based application in research.
Education Qualification
| Name of the Degree | Year of Passing | Institute/University |
|---|---|---|
| B.E | 2009 | Samrat Ashok Technological Institute Vidisha M.P |
| M.E | 2011 | Shri Govindram Seksaria Institute of Technology and Science Indore M.P |
| Ph.D. (VLSI Design) | 2018 | PDPM Indian Institute of Information Technology, Design & Manufacturing Jabalpur M.P |
Teaching Experience
| Programme Name | Department And Organization | From | To | Total Experience |
|---|---|---|---|---|
| Assistant professor | Electronics and Communication Engineering, NIT Hamirpur, Himachal Pradesh | 10/12/2018 | Till date |
Administrative Experience
| Position Held | Department And Organization | From | To |
|---|---|---|---|
| Assistant Faculty In charge | Central Security Institute, NIT Hamirpur, Himachal Pradesh | 20/12/2018 | 03/08/2020 |
| Assistant Warden | Himadri Boys Hostel, NIT Hamirpur, Himachal Pradesh | 26/03/2019 | 01/06/2020 |
| Assistant Faculty In charge | Sports & Yoga Activities | 10/04/2019 | 03/08/2020 |
| Assistant Warden | Higiri Boys Hostel, NIT Hamirpur, Himachal Pradesh | 01/06/2020 | 03/08/2020 |
| Departmental Faculty Incharge, SPEC Society | E&CED, NIT Hamirpur, Himachal Pradesh | 21/08/2019 | |
| Departmental Faculty Incharge, VLSI and Nano Lab | E&CED, NIT Hamirpur, Himachal Pradesh | 21/08/2019 | 04/03/2020 |
| Departmental Faculty Incharge, Embedded System Lab | E&CED, NIT Hamirpur, Himachal Pradesh | 04/03/2020 |
Research Experience
| Research Interests : | Tunnel FET, Multigate MOSFET, Solid-State Devices, Semiconductor Devices: Physics, Simulation and modelling of nanoscale devices for low power and high frequency applications, Circuit level implementation of devices in nanoelectronics, Low-power MOSFET and TFETs. | |
| Brief Research Statement : | Requirement of energy efficient transistor which supports for high frequency ultra low power application. Need of smaller off-currents and standby power dissipation. Need of lesser switching delay which improves circuit level performances. Reducing supply voltage (VDD) while keeping leakage current low is one of the major concern for minimizing energy consumption. The thermal limit of MOSFET sub threshold swing (SS) restricts lowering threshold voltage (Vt), causing significant performance degradation at low VDD. Need of scaling in devices with reduced gate leakage. |
Research Projects
| Role | Project Type | Title | Funding Agency | From | To | Amount | Status | Co-Investigator | Sanction Order | Sanction Date |
|---|
Journal Publications
| Year | Author(s) | Journal Name | Title & Vol. No. | Indexing (SCI/Web of science/Scopus) |
|---|---|---|---|---|
| 2018 | D. S. Yadav, D. Sharma, S.Tirkey, D. G. sharma, S. Bajpai, D. Soni, S. Yadav, Mohd. Aslam and N. Sharma | IET, Micro Nano Letters | Hetero-material CPTFET with high-frequency and linearity analysis for ultra-low power applications, doi: 10.1049/mnl.2018.5075 Accepted on 11 July. 2018 | SCI |
| 2018 | D. S. Yadav, A. Verma, D. Sharma, and N. Sharma | Superlattices and Microstructures, Elsevier | Study of Metal Strip Insertion and its Optimization in Doping Less TFET. Vol. no. 122, pp. 577-586, Oct 2018 | SCI |
| 2018 | D. S. Yadav, D. Sharma, S. Tirkey, and V. Bajaj | Journal of Computational Electronics, Springer | A systematic investigation for performance improvement by integrated effect of gate under lapping, dual work functionality and hetero gate dielectric for CPTFET vol. 17, Issue. 1, pp 118-128, Mar 2018 | SCI |
| 2017 | D. S. Yadav, A. Verma, D. Sharma, S. Tirkey, and B.R. Raad | Superlattices and Microstructures, Elsevier | Comparative investigation of novel hetero gate dielectric and drain engineered charge plasma TFET for improved DC and RF performance vol. 111, pp. 123-133, Nov. 2017 | SCI |
| 2017 | D. S. Yadav, D. Sharma, A. Kumar, D. Rathor, R. Agrawal, S. Tirkey, B. R. Raad, and V. Bajaj, | IET, Micro Nano Letters | Performance investigation of hetero material (InAs/Si) based charge plasma TFET vol.12, no.6, pp.358–363, Jan. 2017 | SCI |
| 2016 | D. S. Yadav, B. R. Raad, and D. Sharma | Superlattices and Microstructures, Elsevier | A novel gate and drain engineered charge plasma tunnel field-effect transistor for low sub-threshold swing and ambipolar nature,” vol. no. 100, pp. 266–273, Dec. 2016 | SCI |
| 2016 | D. S. Yadav, D. Sharma, B.R. Raad, V. Bajaj, | Superlattices and Microstructures, Elsevier | “Impactful Study of Dual Work Function, Underlap and Hetero Gate Dielectric on TFET with Different Drain Doping Profile for High Frequency Performance Estimation and Optimization,” vol. no. 96, pp. 36–46, Aug. 2016 | SCI |
| 2018 | S. Tirkey, D. Sharma, B. Raad, D. S. Yadav | IEEE Transaction on Electron Devices | A Novel Approach to Improve the Performance of Charge Plasma Tunnel Field Effect Transistor" vol. 65, no.1, pp. 282-289, Jan. 2018. | SCI |
| 2017 | S. Tirkey, D. Sharma, D. S. Yadav, and S. Yadav | IEEE Transaction on Electron Devices | Analysis of a Novel Metal Implant Junctionless Tunnel Field-Effect Transistor for Better DC and Analog/RF Electrostatic Parameters, vol. 63, no.9, pp. 3943-3950, Sep. 2017 | SCI |
| 2017 | M. Verma, S. Tirkey, S. Yadav, D. Sharma, and D.S. Yadav | IEEE Transaction on Electron Devices | Performance Assessment of a Novel Vertical Dielectrically Modulated TFET-Based Biosensor. vol. 63, no. 9, pp. 3841-3848, Sep. 2017 | SCI |
| 2016 | B. R. Raad, D. Sharma, P. Kondekar, K. Nigam, and D. S. Yadav | IEEE Transaction on Electron Devices | Drain work function engineered doping-Less charge plasma TFET for ambipolar suppression and RF performance improvement: A proposal design and investigation", vol. 63, no. 10, pp. 3950-3957, Oct. 2016 | SCI |
| 2016 | D. Singh, D. Sharma, S. Pandey, K. Nigam, D. S. Yadav and P. N. Kondekar | IEEE Transaction on Electron Devices | A Charge Plasma based Dielectric Modulated Junctionless TFET for Biosensor Label Free Detection. vol. 64, no. 1, pp. 271-278, Jan. 2016 | SCI |
| 2017 | S. Tirkey, B. R. Raad, D. Sharma, and D. S. Yadav | Journal of computational electronics Springer | Introduction of a metal strip in oxide region of junctionless tunnel field-effect transistor to improve DC and RF performance,” vol. no. 16, Issue. 3, pp 714- 720 Sep. 2017. | SCI |
| 2016 | D. Sharma, B. R. Raad, D.S. Yadav, P. Kondekar, and K. Nigam | IET, Micro Nano Letters | 2-D Potential, Electric Field and Drain Current Model of Source Pocket Hetero Gate Dielectric Triple Work Function Tunnel Field-Effect Transistor. vol. 12, no. 1, pp. 11-16, Sep. 2016 | SCI |
| 2018 | A Lemtur, D Sharma, P Suman, J Patel, D S Yadav and N Sharma | Superlattices and Microstructures, Elsevier | Performance analysis of gate all around GaAsP/AlGaSb CPTFET,” vol. no. 117, pp. 364–372, Mar. 2018 | SCI |
| 2018 | S Gupta, D Sharma , D Soni , S Yadav ; M. Aslam , D S Yadav, K Nigam, N Sharma | IET, Micro Nano Letters | Examination of the impingement of interface trap charges on heterogeneous gate dielectric dual material control gate tunnel field effect transistor for the refinement of device reliability. Vol. no. 13 , Issue: 8 pp: 1192 - 1196, 2018 | SCI |
| 2018 | M. Aslam, D Sharma, D Soni, S Yadav , B R Raad , D S Yadav , N Sharma | IET, Micro Nano Letters | Effective design technique for improvement of electrostatics behaviour of dopingless TFET: proposal, investigation and optimisation. Year: 2018 , Vol. no. 13 , Issue: 10 pp 1480 - 1485, 2018 | SCI |
| 2018 | S Tirkey, D S yadav, D Sharma | Applied Physics A, Springer | Controlling ambipolar current of dopingless tunnel field-effect transistor https://doi.org/10.1007/s00339-018-2237-6 | SCI |
| 2019 | D. Soni, A. K. Behra, D.Sharma, D.P.Samajdar, D.S.Yadav | Journal of Nanoelectronics and Optoelectronics | Structural Modification of Doped Tunnel Field Effect Transistor for Enhanced Conduction Current and Lower Subthreshold Swing.Year: 2019 , Vol. no. 14 , Issue: 11 pp 1539-1547, 2019 | SCI |
| 2020 | A. Lodhi, C. Rajan, A.K. Behera, D.P.Samajdar, D. Soni, D. S. Yadav | Applied Physics A, Springer | Sensitivity and sensing speed analysis of extended nano-cavity and source over electrode in Si/SiGe based TFET biosensor | SCI |
| 2021 | A.Dixit, D.P. Samajdar, N. Bagga, D. S. Yadav | Materials Today Communications Elsevier | Performance investigation of a novel GaAs1-xSbx-on-insulator (GASOI) FinFET: Role of interface trap charges and hetero dielectric | SCI |
| 2021 | N. Parmar, P. Singh, D. P. Samajdar, D. S. Yadav | Applied Physics A, Springer | Temperature impact on linearity and analog/RF performance metrics of a novel charge plasma tunnel FET | SCI |
| 2021 | P. Singh, D. S. Yadav | Applied Physics A, Springer | "Impact of temperature on analog/RF, linearity and reliability performance metrics of tunnel FET with ultra‑thin source region" | SCI |
| 2021 | P. Singh, D. S. Yadav | Silicon, Springer | Impactful Study of F-shaped Tunnel FET | SCI |
| 2021 | S. Kumar, D. S. Yadav | Applied Physics A, Springer | Temperature analysis on electrostatics performance parameters of dual metal gate step channel TFET | SCI |
| 2021 | A. K. Behera, C. Rajan, D. P. Samajdar, A. Lodhi, J. Patel, K. Mishra & D. S. Yadav | Journal of Electronic Materials, Springer | Performance Analysis of Sigma Delta ADC Developed using Electrically Doped GAPSb/InP Gate All Around Tunnel Field Effect Transistor | SCI |
| 2021 | P. Singh, D. S. Yadav | Silicon, Springer | Design and Investigation of F-shaped Tunnel FET with Enhanced Analog/RF Parameters | SCI |
| 2021 | M. Kamal, D. S. Yadav | Silicon, Springer | Effects of linearity and reliability analysis for HGO-DW-SCTFET with temperature variation for high frequency application | SCI |
Conference Publications
| Year | Author(s) | Conference | Title | Indexing |
|---|---|---|---|---|
| 2018 | D. S. Yadav, D. Sharma, D. G. Sharma and S. Bajpai | IEEE’s 3rd International Conference for Convergence in Technology (I2CT), .sponsored by IEEE Bombay Section, held from 6th — 8th April, 2018, at Hotel Gateway (TAJ), Hinjewadi, Pune, Maharashtra , India | High Frequency Analysis of GaAsP/InSb Hetero Junction Double Gate Tunnel Field Effect Transistor | SCI / IEEE International |
| 2017 | D. S. Yadav, D. Sharma, S. Tirkey, D. Soni, D. G. Sharma and S. Bajpai | IEEE International Symposium on Nanoelectronics and Information Systems (IEEE iNIS- 2017), held from18th —20th Dec, 2017, at OIST Bhopal, India. | A Comparative Study of GaP/SiGe heterojunction double gate Tunnel Field Effect Transistor | SCI / IEEE International |
| 2017 | D. Soni, D. Sharma, S. Yadav, Mohd. Aslam and D. S. Yadav | IEEE International Symposium on Nanoelectronics and Information Systems (IEEE iNIS-2017), held from 18th—20th Dec, 2017, at OIST Bhopal, India | Gate metal work function engineering for the improvement of electrostatic behaviour of doped tunnel field effect transistor | SCI / IEEE International |
| 2017 | D. S. Yadav, D. Sharma, R. Agrawal, G. Prajapati, S. Tirkey, B. R. Raad, and V. Bajaj | IEEE International Conference on Information Communication Instrumentation and Control (ICICIC -2017), held from 17th -19th Aug, 2017, at Medi-caps University Indore India | Temperature based performance analysis of doping-less Tunnel Field Effect Transistor | SCI / IEEE International |
| 2017 | S. Tirkey, D. S. Yadav, D. Sharma and V. Bajaj | IEEE International Conference on Information Communication Instrumentation and Control (ICICIC -2017), held from 17th -19th Aug, 2017, at Medi-caps University Indore India. | Controlling Ambipolar Behavior and Improving Radio Frequency Performance of Hetero Junction Double Gate TFET by Dual Work-Function, Hetero Gate Dielectric, Gate Underlap: Assessment and Optimization | SCI / IEEE International |
| 2016 | D. S. Yadav, D. Sharma, B. R. Raad and V. Bajaj | IEEE international conference on advanced communication control and computing technologies (ICACCT 2016) organized by Syed Ammal Engineering College held from 25th -27th May,2016, at Ramanathapuram, Tamilnadu, India | Dual Workfunction Hetero Gate Dielectric Tunnel Field-Effect Transistor Performance Analysis | SCI / IEEE International |
| 2020 | N. Parmar ; D. S. Yadav ; S. Kumar ; R. Sharma ; S. Saraswat ; A. Kumar | 2020 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS) held at MANIT Bhopal | Performance Analysis of a Novel Dual Metal Strip Charge Plasma Tunnel FET | SCI / IEEE International |
| 2020 | S. Saraswat ; D. S. Yadav ; S. Kumar ; N. Parmar ; R. Sharma ; A. Kumar | 2020 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS) held at MANIT Bhopal | Performance Analysis of TMG FinFETs for Low Power Application with Improved Analog/RF Characteristics | SCI / IEEE International |
| 2020 | R. Sharma ; D. S. Yadav; S. Kumar ; N. Parmar ; S. Saraswat ; A. Kumar | 2020 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS) held at MANIT Bhopal | Novel Perspective Approach to Improve Performance of Nanowire TFET | SCI / IEEE International |
| 2020 | S. Kumar ; D. S. Yadav ; S. Saraswat ; N. Parmar ; R. Sharma ; A. Kumar | 2020 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS) held at MANIT Bhopal | A Novel Step-Channel TFET for Better Subthreshold Swing and Improved Analog/RF Characteristics | SCI / IEEE International |
| 2021 | P. Singh, D. S. Yadav .et.al | IEEE, 2021 6th International Conference for Convergence in Technology (I2CT), 2021 | Doping and Dopingless Tunnel Field Effect Transistor | SCI / IEEE International |
| 2021 | P. Singh, D. S. Yadav et.al | IEEE, 2021 6th International Conference for Convergence in Technology (I2CT), 2021 | A Low Power Single Gate L-shaped TFET for High Frequency Application | SCI / IEEE International |
| 2021 | M. Kamal, D. S. Yadav | Springer, 4th International Conference on Inventive Material Science and Applications (ICIMA- 2021) | A Comparative Analysis with Impact of Work Function Engineering of Step Channel TFET | SCI / International |
| 2021 | P. K. Pandey, D. S. Yadav | IEEE, 5th International Conference on Trends in Electronics and Informatics (ICOEI 2021) | Parametric Inspection of 6T SRAM Cell | SCI / IEEE International |
| 2021 | R.Sharma, D. S. Yadav | International Conference on Communication, Control and Information Sciences (ICCISc), 2021 | Temperature dependence of Linearity and RF Performance metrics in DMG GaSb-Si Nanowire TFET | SCI / IEEE International |
| 2021 | R. Sharma, D. S. Yadav | International Conference on Communication, Control and Information Sciences (ICCISc), 2021 | Interface Trap Charges and their impact on Linearity and RF Performance metrics for a Heterodielectric Dual Metal Gate GaSb-Si Nanowire TFET | SCI / IEEE International |
| 2021 | S. Saraswat, D. S. Yadav | International Conference on Communication, Control and Information Sciences (ICCISc), 2021 | Impact of Interface Trap Charge on Analog/RF parameters of Novel Heterogeneous Gate Dielectric Tri-Metal Gate FinFET | SCI / IEEE International |
| 2021 | R. M. Gangadari, D. S. Yadav | First International Conference on Advances in Computing and Future Communication Technologies (ICACFCT-2021) | Extraction and Comparative Inspection of several parameters of 6T, 8T, 10T SRAM | SCI / IEEE International |
| 2021 | V. Choudhary, D. S. Yadav | "5th International Conference on Electronics, Communication and Aerospace Technology (ICECA 2021) " | Analyses of Power, Delay and SNM of 6T & 8T SRAM Cells | SCI / IEEE International |
Book/Chapters Written
| Type (Book/Chapter) | Author(s) | Title | Publisher | ISBN/ISSN No. | Year |
|---|
Research Supersion
| Programme Name | Scholar Name | Research Topic | Status | Year | Co-Superivisor(s) |
|---|---|---|---|---|---|
| M.Tech | Somya Saraswat | Performance Analysis of Tri-Metal Gate (TMG) FinFETs for low power applications | Completed | 2020 | - |
| M.Tech | Nitesh Parmar | Charge Plasma Tunnel FET: Proposal, Design and Investigation | Completed | 2020 | - |
| M.Tech | Sachin Kumar | Impactful Study of TFET for High Frequency Performance Estimation and Optimization | Completed | 2020 | - |
| M.Tech | Ritwik Sharma | Comprehensive Study of Nanowire Tunnel Field Effect Transistor | Completed | 2020 | - |
| M.Tech | Prince Kumar Pandey | Parametric Analysis of Different SRAM Cells and Designing 4x4 Array | Completed | 2021 | - |
| M.Tech | Manshi Kamal | Analysis of Analog/RF and Linearity Performance for Step Channel Tunnel Field Effect Transistor | Completed | 2021 | - |
| M.Tech | Sangeeta Pandey | Design and performance estimation of 12T SRAM cell on CMOS technology with stability analysis | Completed | 2021 | - |
| M.Tech | Ayush Sharma | Investigation of Drain Engineering based CPTFET | Completed | 2022 | - |
| M.Tech | Vibhash Choudhary | Optimization of SRAM Cells with CMOS Technology | Completed | 2022 | - |
| M.Tech | Rakesh Murthy Gangadari | Design and Investigation of CMOS and TFET based SRAM Memory cell for low power application | Completed | 2022 | - |
| M.Tech | Prajwal Roat | Design and assessment of Tunnel FET with various Engineering Techniques | Completed | 2022 | - |
| Ph.D | Prabhat Singh | Design and investigation of Tunnel FET for low power based circuit application | Ongoing | 2019 | - |
Patents
| Name | Reg./Ref.No. | Date of Award/Filling | Awarding Agencies | Status |
|---|
Conferences/Workshop/Courses Organized
| Category | Type | Title | Venue | From | To | Designation |
|---|---|---|---|---|---|---|
| fdp | National-NKN FDP (Sponsored by E&ICT Academy, IIT Guwahati) | Antenna Trends | National Institute of Technology Hamirpur | 01/07/2019 | 05/07/2019 | Course Coordinator |
| fdp | National-NKN FDP (Sponsored by E&ICT Academy, IIT Roorkee) | VLSI Chip Design Hands on using open source EDA | National Institute of Technology Hamirpur | 08/07/2019 | 12/07/2019 | Course Coordinator |
| stc | National (Sponsored by IRDT Kanpur UP) | Future Aspect of Electronics and Digital Learning | National Institute of Technology Hamirpur | 16/09/2019 | 21/09/2019 | Course Coordinator |
| workshop | National | Design Challenges of IoT with AI & ML Applications | National Institute of Technology Hamirpur | 30/11/2020 | 04/12/2020 | Convener & Coordinator |
| fdp | National (Sponsored by ATAL AICTE) | Internet of Things | National Institute of Technology Hamirpur | 01/06/2021 | 05/06/2021 | Course Coordinator |
| workshop | National | Intelligent Device Computing, Communication and Signal Processing | National Institute of Technology Hamirpur | 10/01/2022 | 14/01/2022 | Course Coordinator |
Expert Talks
| Title | Place | Year | Description of Event |
|---|
Consultancy
| Title of Consultancy | Client Organization | Faculty Involved | Amount(INR) | Status |
|---|
International and National Exposure
| Sr.No. | Title | Description |
|---|
Honors & Recognitions Achieved
| Sr.No. | Title | Activity | Given By | Year |
|---|---|---|---|---|
| 1 | 3D Networking and Collaborative Environment for Online Education | Best Paper Award | 10th International Conference on Emerging Trends in Engineering and Technology - Signal and Information Processing (ICETET-SIP-22) held at G H Raisoni College of Engineering, Nagpur during 29th - 30th April 2022, technically supported by IEEE Bombay Section and Nagpur Sub-Section in association with GHR Lab and Research Center | 2022 |
| 2 | Cloud based psychopathology companion | Best Paper Award | 10th International Conference on Emerging Trends in Engineering and Technology - Signal and Information Processing (ICETET-SIP-22) held at G H Raisoni College of Engineering, Nagpur during 29th - 30th April 2022, technically supported by IEEE Bombay Section and Nagpur Sub-Section in association with GHR Lab and Research Center | 2022 |