profile

Prof. (Mrs.) Rajeevan Chandel

Professor

Prof. Rajeevan Chandel was awarded Ph.D. degree from Indian Institute of Technology (IIT) Roorkee, India, under QIP scheme of Govt. of India in 2005. She received M. Tech. degree in Integrated Electronics and Circuits from IIT Delhi, India, in 1997. She received B.E. degree in E&CE from TIET (Thapar University) Patiala, India, in 1990. She is a double gold medalist of Himachal Pradesh University, Shimla, India, in Pre-University and Pre-Engineering in 1985 and 1986, respectively. She joined the Department of Electronics and Communication Engineering, NIT Hamirpur, HP India, as a lecturer in August 1990, where presently she is working as a Professor and has been the Head of the Department for two tenures. Dr. Chandel has been DEAN (Research & Consultancy), and DEAN (Academic), NIT Hamirpur HP. Her research interests are Low Power VLSI Design, Interconnect Design & others.

Name : Prof. (Mrs.) Rajeevan Chandel
Designation : Professor
Department : Electronics & Communication Engineering
Qualification : Ph.D. (IIT Roorkee), M.Tech. (IIT Delhi), B.E. (TIET, Patiala)
Phone : 254624
Email ID : rchandel@nith.ac.in
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General Information



Name : Prof. (Mrs.) Rajeevan Chandel
Designation : Professor
Department : Electronics & Communication Engineering
Qualification : Ph.D. (IIT Roorkee), M.Tech. (IIT Delhi), B.E. (TIET, Patiala)
Date of Birth : 11/27/1968
Date of joining : 08/17/1991

Contact Details

Phone : 254624
Email ID : rchandel@nith.ac.in

Specialization

Position Held



Position Department Name Institute Name Time Period

Educational Qualification



Name of the Degree Year of Passing Institute/University
1. Matriculation (ICSE Board) 1984 Sacred Heart High School Sidhpur, Dharamshala, Himachal Pradesh
2. Pre-University Class 1985 DAV College, Kangra, HP University
3. Pre-Engineering 1986 DAV College, Kangra, HP University
4. B.E. (Electronics and Communication Engineering) 1990 Thapar Institute of Engineering & Technology (now Thapar University), Patiala, Pb
5. M.Tech. (Integrated Electronics & Circuits) 1997 Indian Institute of Technology (IIT), Delhi
6. Ph.D. (Low-Power VLSI Design) 2005 Indian Institute of Technology (IIT), Roorkee

Honors & Recognitions Achieved



Sr.No. Title Activity Given By Year
1 Appreciation Letter from Director NIT Hamirpur HP, vide No. NIT-HMR-DIRECTOR-DO-339, DATED 23rd June 2007, for doing excellently well as Head & Faculty of E&CED NIT Hamirpur and helping attain 20th Rank for NIT Hamirpur as per Data Quest Ranking, also published in Hindustan Times RECOGNITION - Appreciation Letter Director NIT Hamirpur HP 2007
2 Appreciation Letter from Director NIT Hamirpur HP in August 2007, for being a member of SSC & thereby smooth conduct of Interviews of the E&CED & CSED NIT Hamirpur in 2007 RECOGNITION - Appreciation Letter Director NIT Hamirpur HP 2007
3 BEST FACULTY AWARD E&CE 2006-2007 NIT Hamirpur, Conferred by Director NIT Hamirpur HP at 2nd Convocation held on 5th Jan 2008 HONOUR - AWARD Director NIT Hamirpur HP 2008
4 Appreciation Letter from Registrar NIT Hamirpur HP in Feb 2008, for being awarded FIVE-Years (A+ Grade) National accreditation to the E&CE Department wef 22 Jan 2008 Recognition- Appreciation Letter Registrar NIT Hamirpur (HP) 2008
5 The Best Citizens of India Award 2009, International Publishing House for academic and research contribution Honour - Award International Publishing House 2009
6 Session Chair, Member of Advisory & Technical Committees, Key-note Speaker of various National Conferences Recognition - Appreciation Chairs of various Conferences 2006 onwards 2006
7 IETE - PROF KS KRISHNAN MEMORIAL AWARD for BEST PAPER in IETE Technical Review in 2016, awarded on 17 Sep 2017 in IETE Convention, Kochi, India HONOUR - Prestigious AWARD IETE (India) 2017
8 Secured DISTINCTION and MERIT Scholarship in B.E. Also won INSTITUTE COLOUR-1989 for co-curricular activities Recognition - Appreciation Director TU 1989
9 Topped in HPU, Shimla in Pre-Engineering 1986. Also won University GOLD- MEDAL and National Merit Scholarship HONOUR - AWARD & GOLD MEDAL VC HPU
10 Topped in HPU, Shimla in Pre-University Class 1985, also Awarded University GOLD-MEDAL HONOUR - AWARD & GOLD MEDAL VC HPU
11 Head Girl of Sacred Heart High School, Sidhpur, Dharmsala for the year 1983-84 HONOUR - AWARD Principal

Research Experience



Research Interests : Low-Power VLSI Design, VLSI Interconnect Design, Nano-electronics, MEMS, Electronic Device Modeling and Simulation
Brief Research Statement : Dedicated towards students, academic fraternity, society and community, my vision is to see India excel in all areas of VLSI Design, Electronics and Communication Engineering. Low Power CMOS VLSI Design is my core research area. The various aspects of modeling and simulation of VLSI interconnects, devices & circuits, and ASIC design are the other major areas of my research work.

Journal Publications



Year Author(s) Title & Vol. No. Journal Name Indexing (SCI) Web of Science/Scopus
2005 Rajeevan Chandel, S. Sarkar and R.P. Agarwal Performance Controlling Parameters of Voltage-Scaled Repeaters for Long Interconnections, vol. 51, no. 2, pp. 107-113 IETE Journal of Research, Taylor & Francis SCIE
2005 Rajeevan Chandel, S. Sarkar and R.P. Agarwal Transition Time Considerations in Voltage-Scaled Repeaters, vol. 22, no. 3, pp.39-40 Microelectronics International, Emerald, UK. SCI
2000 Rajeevan Chandel and Ashwani Kumar Design and Development of Dielectric based Electrostatic Microactuators, vol.46, no. 4, pp. 261-264 IETE Journal of Research Taylor & Francis SCIE
2005 Rajeevan Chandel, S. Sarkar and R.P. Agarwal Delay Analysis of a Single Voltage-Scaled-Repeater driven Long Interconnect, vol. 22, no. 3, pp. 28-33 Microelectronics International, Emerald, UK. SCI
2005 Rajeevan Chandel, S. Sarkar and R.P. Agarwal Repeater insertion in global interconnects in VLSI circuits, vol. 22, no. 1, pp. 43-50 Microelectronics International, Emerald Pub. UK. SCI
2006 Rajeevan Chandel, S. Sarkar and R.P. Agarwal Repeater stage timing analysis for VLSI resistive interconnects, vol. 23, no. 3, pp. 19-25 Microelectronics International, Emerald UK. SCI
2007 Rajeevan Chandel, S. Sarkar and R.P. Agarwal An Analysis of Interconnect Delay Minimization by Low-Voltage Repeater Insertion, vol. 38, no. 4-5, pp 649-655 Microelectronics Journal, Elsevier Science SCI
2007 Rajeevan Chandel, S. Sarkar, and Ashwani K. Chandel Investigations on Short-Circuit Power Dissipation in Repeater Loaded VLSI Interconnects, vol. 3, no. 3, pp. 337–344 Journal of Low Power Electronics, ASP, USA. Scopus
2007 Rajeevan Chandel, S. Sarkar and R.P. Agarwal Delay and Power Management of Voltage-Scaled Repeaters for Long Interconnects, vol. 27, no. 4, pp. 333-339 International Journal of Modelling & Simulation, Taylor & Francis. Scopus
2008 Rajeevan Chandel, Y. Nataraj, G. Khanna Performance Analysis of Voltage-Scaled Static and Dynamic CMOS Circuits, vol.3, no.2, pp. 171-176 Journal of Nanoelectronics & Optoelectronics (JNO), ASP, USA SCI
2009 Gargi Khanna, Rajeevan Chandel, Ashwani K. Chandel, S. Sarkar Analysis of non-ideal effects in coupled VLSI interconnects with active and passive load variation, vol. 26, no. 1, pp. 3-9 Microelectronics International, Emerald UK. SCI
2010 Ashutosh Nandi, Rajeevan Chandel Design and Analysis of Sub-DT Sub-Domino Logic Circuits for Ultra Low Power Applications, vol. 6, No. 4, pp. 513-520 Journal of Low Power Electronics, ASP, USA Scopus
2010 Kiran K. Chaddha, Rajeevan Chandel Design and Analysis of a Modified Low Power CMOS Full Adder Using Gate-Diffusion Input Technique, vol. 6, No. 4, pp. 482-490 Journal of Low Power Electronics, ASP, USA Scopus
2011 Sandeep Singh Gill, Rajeevan Chandel, Ashwani K. Chandel Efficient Clustering and Simulated Annealing Approach for Circuit Partitioning, vol.16, No. 6, pp. 708-712 Journal of Shanghai Jiaotong Univ. (Science), Elsevier Scopus
2012 Rohit Dhiman, Rajeevan Chandel Delay Analysis of a CMOS Buffer Driven RLC Interconnect Load for Sub-Threshold Applications, vol. 32, no.1, pp. 18-23 International Journal of Modelling and Simulation, Taylor & Francis. Scopus
2012 Rohit Dhiman, Rajeevan Chandel Sub-Threshold Delay and Power Analysis of CMOS Buffer Driven Interconnect Load for Ultra Low Power Applications, vol. 8, no. 1, pp. 39-46 Journal of Low Power Electronics, ASP, USA Scopus
2014 Rohit Dhiman, Rajeevan Chandel Crosstalk analysis of CMOS buffer driven interconnects for ultra-low power applications, vol. 13, no. 2, pp. 360-369 Journal of Computational Electronics, Springer. SCI
2015 Rohit Dhiman and Rajeevan Chandel Dynamic crosstalk analysis in coupled interconnects for ultra-low power applications, vol. 34, no. 1, pp. 21–40 Circuits, Systems and Signal Processing, Springer, USA. SCI
2015 Rohit Dhiman, Rohit Sharma and Rajeevan Chandel Compact models and delay computation of sub-threshold interconnect circuits, vol. 84, no.1, pp. 53-65 Analog Integrated Circuits & Signal Processing, Springer, USA. SCI
2015 Sunil Jadav, Munish Vashistah, Rajeevan Chandel RLC equivalent RC delay model for global VLSI interconnect in current mode signalling, vol. 35, no. 1, pp. 27–34 International Journal of Modelling and Simulation, Taylor & Francis, Scopus
2015 Rohit Dhiman and Rajeevan Chandel Compact models and computation of crosstalk for sub-threshold interconnect circuits, vol. 82, no.3, pp. 637–652 Analog Integrated Circuits & Signal Processing, Springer , USA. SCI
2016 Yash Agrawal and Rajeevan Chandel Crosstalk Analysis of Current-Mode Signalling-Coupled RLC Interconnects Using FDTD Technique**, vol. 33, no. 2, pp. 148-159 IETE Technical Review, Taylor & Francis. **(IETE- KS KRISHNAN MEMORIAL AWARD (2017) Awarded to Yash Agrawal & Dr. Rajeevan Chandel for Best System Oriented Paper) SCIE
2017 Yash Agrawal, M. Girish Kumar and Rajeevan Chandel A Novel Unified Model for Copper and MLGNR Interconnects Using Voltage- and Current-Mode Signaling Schemes, vol. 59, no. 1, pp. 217-227 IEEE Transactions on Electromagnetic Compatibility. SCI
2017 M. Girish Kumar, Y. Agrawal, and Rajeevan Chandel Modelling and Performance Analysis of Dielectric Inserted Side Contact Multilayer Graphene Nanoribbon Interconnects, vol. 11, no. 3, pp. 232-240, May 2017 IET Circuits, Devices and Systems SCI
2018 M. Girish Kumar, Rajeevan Chandel, and Y. Agrawal An Efficient Crosstalk Model for Coupled Multi-Walled Carbon Nanotube Interconnects, vol. 60, no. 2, pp. 487 – 496 IEEE Transactions on Electromagnetic Compatibility SCI
2018 Yash Agrawal, M. G. Kumar, and Rajeevan Chandel A Unified Delay, Power and Crosstalk Model for Current Mode Signaling Multiwall Carbon Nanotube Interconnects,” Paper Circuits, Systems, and Signal Processing, Springer SCIE
2018 Yash Agrawal, M. Girish, and Rajeevan Chandel An efficient and novel FDTD method based performance investigation in high-speed current-mode signaling SWCNT bundle interconnect, vol. 43, no. 175, pp.1-12 Sadhana, Springer Nature SCIE
2019 Sunil Jadav, Rajeevan Chandel High performance 9T adiabatic SRAM and novel stability characterization using pole zero placement, vol. 98, no.2, pp. 347–355, February 2019 (SCI, Impact factor: 0.982) Analog Integrated Circuits and Signal Processing, Springer SCI
2020 Sunil Jadav, Rajeevan Chandel, M. Vashishath Modeling the Impact of Fundamental and Quantum Resistance on the Performance of SWCNT Based RLC Interconnects International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, Wiley, 33:e2698. https://doi. org/10.1002/jnm.2698 Scopus
2021 Neha Sharma, Rajeevan Chandel Variation tolerant and stability simulation of low power SRAM cell analysis using FGMOS, 2150029 International Journal of Modeling, Simulation, and Scientific Computing Scopus
2021 Animesh Srivastava, Rajeevan Chandel A Novel Co-planar Five Input Majority Gate Design in Quantum-Dot Cellular Automata, DOI: 10.1080/02564602.2021.1914205. IETE Technical Review, Taylor & Francis Publication SCIE
2021 Ashish Singh, Rajeevan Chandel, Rohit Dhiman Proposal and analysis of relative stability in mixed CNT bundle for sub-threshold interconnects, online 20 May Integration- the VLSI Journal, Elsevier SCIE
2021 Sunil Jadav, Shubham Tayal, Rajeevan Chandel, M. Vashishath High speed RLC equivalent RC delay model using normalized asymptotic function for global VLSI interconnects, https://doi.org/10.1016/j.mejo.2020.104941, vol. 107, pp. 104941 Microelectronics Journal, Elsevier SCIE, Scopus
2020 C. Ranga, A. Kumar, Rajeevan Chandel Influence of electrical and thermal ageing on the mineral insulating oil performance for power transformer applications, vol. 62, no. 4, pp. 222-231, 2020. Insight-Non-Destructive Testing and Condition Monitoring Scopus
2019 Sunil Jadav, Munish Vashistah, Rajeevan Chandel High speed RLC equivalent RC delay model for global VLSI interconnects, First Online: 22 January 2019. Doi:10.1007/s10470-019-01398-x, vol. 100, no.1, pp. 109–117, July 2019. Analog Integrated Circuits and Signal Processing, Springer USA SCI
2017 C. Ranga, Ashwani Kumar, and Rajeevan Chandel Condition assessment of power transformers based on multi-attributes using fuzzy logic, vol.11, no.8, pp. 983–990, 2017, July 2017 IET Science Measurements and Technology SCI
2017 Rohit Dhiman and Rajeevan Chandel Delay analysis of buffer inserted sub-threshold interconnects, vol. 90, no. 2, pp. 435-445, 2017. Analog Integrated Circuits and Signal Processing SCI
2017 Yash Agrawal, Rajeevan Chandel, and Rohit Dhiman Variability Analysis of Stochastic Parameters on the Electrical Performance of On-Chip Current-Mode Interconnect System, vol. 63, no.2, pp. 268-280, 2017. IETE Journal of Research, Taylor & Francis SCI
2018 C. Ranga, Ashwani Kumar, and R. Chandel Performance analysis of alternative solid dielectrics of transformers with a blend of mineral and silicon oils, vol. 35, no. 4, pp. 331-341, 2018 IETE Technical Review, Taylor & Francis SCIE
2016 V. Basetti, Ashwani Kumar Chandel, and Rajeevan Chandel Power system dynamic state estimation using prediction based evolutionary technique, vol. 107, pp. 29-47, 2016. Energy SCI
2016 Yash Agrawal, M. Girish Kumar, and Rajeevan Chandel A comprehensive model for high-speed current-mode signaling in next generation MWCNT bundle interconnect using FDTD technique, vol. 15, no. 4, pp. 590-598, 2016. DOI: 10.1109/TNANO.2016.2558475 IEEE Transactions on Nanotechnology SCI
2015 Rohit Dhiman, Rohit Sharma and Rajeevan Chandel Compact models and delay computation of sub-threshold interconnect circuits, DOI 10.1007/s10470-015-0557-4, vol. 84, no.1, pp. 53-65, 2015 Analog Integrated Circuits & Signal Processing, Springer, USA SCI
2015 Sunil Jadav, Munish Vashistah, Rajeevan Chandel RLC equivalent RC delay model for global VLSI interconnect in current mode signalling, http://dx.doi.org/ 10.1080/02286203.2015.1077009, vol. 35, no. 1, pp. 27–34, 2015. International Journal of Modelling and Simulation, Taylor & Francis Scopus
2021 Mekala Girish Kumar, Yash Agrawal, Vobulapuram Ramesh Kumar, Rajeevan Chandel A prominent unified crosstalk model for linear and sub-threshold regions in mixed CNT bundle interconnects,” https://doi.org/10.1016/j.mejo.2021.105294, vol. 118, no.105294, pp. 1-11, 2021. Microelectronics Journal, Elsevier SCIE, Scopus, IF=1.609
1994 Ashwani Kumar Chandel, Rajeevan Chandel and J.S. Saini Enhancement of Placement Activities in Remotely Located Technical Institutes, vol. 17, no. 3, pp. 32-36, July-September, 1994. ISTE Journal of Education, ISTE Pub.
2001 Rajeevan Chandel “VLSI Micro-fabrication Technologies and MEMS, vol. 42, nos. 1-4, pp. 33-41, January-December 2001. IETE Journal of Education Taylor & Francis Pub.
2007 Rajeevan Chandel Design Techniques for VLSI and Communication DTVC-2007, vol. 3, no. 2, pp. 25, August 2007. VSI Vision, http://vlsi-india.org/ vsi/activities/events.html VSI Pub.
2017 Chilaka Ranga, Ashwani Kumar and Rajeevan Chandel Expert system for condition monitoring of power transformers using fuzzy logic, vol. 9, no. 4, pp. 1-16, July 2017. Journal of Renewable and Sustainable Energy, AIP Publishing SCI
2016 M. Girish Kumar, Yash Agrawal, and Rajeevan Chandel Carbon nanotube interconnects—A Promising Solution for VLSI Circuits, DOI: 10.1080/09747338.2016.1158129, vol. 57, no. 2, pp. 46-64, 2016. IETE Journal of Education, Taylor & Francis T&F Publication
2016 Chilaka Ranga, Ashwani Kumar, and Rajeevan Chandel Fuzzy logic expert system for optimum maintenance of power transformers, International Journal of Electrical Engineering and Informatics, IJEEI, vol. 8, no. 4, pp. 836-850, September 2016. International Journal of Electrical Engineering and Informatics SCOPUS
2017 Chilaka Ranga, Ashwani Kumar, and Rajeevan Chandel Performance analysis of cellulose and Nomex impregnated oil filled power transformers, vol. 9, no. 2, pp. 394-406, July 2017. International Journal of Electrical Engineering and Informatics, IJEEI SCOPUS
2014 Philemon Daniel and Rajeevan Chandel Dynamic Ruleset Based Online Concurrent Testing of Functional Faults for Embedded Controllers, ISSN 0033-2097, vol. 90, no. 1, pp. 111-114, 2014. Polish Journal of Electrical Review Przegląd Elektrotechniczny Polish J.
2013 Viveka Paliwal, Rajeevan Chandel, S. Sarkar New Noise Tolerance Improvement Techniques for Dynamic Logic Circuits, Vol.8, No.1, pp. 65-77, 2013. Journal of Active and Passive Electronic Devices (JAPED) Old City Pub.
2012 Sandeep Singh Gill, Rajeevan Chandel, Ashwani K. Chandel Netlist Bipartitioning using Particle Swarm Optimization Technique, Vol. 3, No. 1, pp.1-15, 2012. International Journal of Artificial Intelligence and Soft Computing (IJAISC) Inderscience Pub.

Conference Publications



Year Author(s) Title Conference name with place Indexing (SCI/Web of science/Scopus)
2005 Rajeevan Chandel, S. Sarkar and R.P. Agarwal On mitigating power and delay in VLSI interconnects, pp. 1533 - 1536 IEEE CANADIAN CONFERENCE on Electrical & Computer Engineering, CCECE 2005, Saskatoon, Canada IEEE
1998 Rajeevan Chandel and Ashwani Kumar Chandel, Sources of Environment Pollution and its Control in Rural Areas of HP “Sources of Environment Pollution and its Control in Rural Areas of HP”, Presented and Published in the Proceedings of the 28th ISTE Convention at PAU, Ludhiana, 21-23rd, Nov. 1998 National
2020 Samarth Agarwal, A. Jamwal, A. Haider, P. Dev, Rajeevan Chandel Biometric Based Secured Remote Electronic Voting System. (BEST PAPER AWARD for the entire Session and Conference). 7th IEEE International Conference on Smart Structures and Systems (ICSSS 2020), Saveetha College of Engineering, 23rd & 24th July 2020. (BEST PAPER AWARD for the entire Session and Conference). IEEE
2020 Pawan Kumar Pandel, Dilip Singh, Rajeevan Chandel, Fixed point division using Newton Raphson Algorithm,” Int. Conference on Microelectronics, Computing and Communication System (MCCS-2020) (Online), Int. Conference on Microelectronics, Computing and Communication System (MCCS-2020) (Online), organized by IETE Advanced Regional Telecom Training Centre, BSNL Ranchi, Jharkhand, India, 11-12 July 2020. IETE International
2020 Animesh Srivastava, Rajeevan Chandel Comparative Analysis of Cross Wired Implementation of Digital Function Design in QCA 1st International Conference on Communication, Computing and Signal Processing (CCSP-2020), NIT Jalandhar (Online), 23-24 July, 2020 International
2018 Yash Agrawal, Rajeevan Chandel, Mekala Girish, and Rutu Parekh Contemporary On-chip System Modeling using FDTD in Low Power Regime International IEEE Symposium on Electrical Design of Advanced Packaging and Systems (EDAPS-2018), Chandigarh, India, 16-18 Dec 2018 IEEE
2018 Ashish Singh, Rohit Dhiman, and Rajeevan Chandel Modeling of Mixed CNT Bundle for Sub-threshold Interconnects International IEEE Symposium on Electrical Design of Advanced Packaging and Systems (EDAPS-2018), Chandigarh, India, 16-18 Dec 2018 IEEE
2018 Haritha Yeleti, Mekala Girish Kumar, Rajeevan Chandel, and Yash Agrawal Transient and Crosstalk Analysis of Doped and Dielectric Inserted MLGNR Interconnects International IEEE Symposium on Electrical Design of Advanced Packaging and Systems (EDAPS-2018), Chandigarh, India, 16-18 Dec 2018 IEEE
2017 Rajeevan Chandel, M. Girish Kumar Impact of Parameter Variability on Delay and Power Dissipation in Dielectric Inserted MLGNR Interconnects International Conference on Emerging Trends in Engineering Innovations & Technology Management ICET: EITM-2017, NIT Hamirpur HP, pp. 381-385, 16-18 Dec 2017 International
2021 Samarth Agarwal, Rajeevan Chandel A Comparative Study of Gallium Nitride Field Effect Transistors with Conventional Silicon Devices International Conference on Recent Development on Materials, Reliability, Safety and Environmental Issues (IMRSE–2021), Dr. B R Ambedkar NIT Jalandhar, held from 25-27 June, 2021 International
2021 Sonalika Singh, Rajeevan Chandel Design and Simulation of Low Noise Amplifier using Active Inductor for 100nm CMOS Technology International Conference on Recent Development on Materials, Reliability, Safety and Environmental Issues (IMRSE–2021), Dr. B R Ambedkar NIT Jalandhar, held from 25-27 June, 2021 International
2021 Afreen Haider and Rajeevan Chandel Design and Comparative Analysis of a Single Stage Differential Amplifier using FinFETs and MOSFETs International Conference on Recent Development on Materials, Reliability, Safety and Environmental Issues (IMRSE–2021), Dr. B R Ambedkar NIT Jalandhar, held from 25-27 June, 2021 International
2021 Razda Bisen, Rajeevan Chandel Machine Learning Usage for Decision Making in Automobile Sector International Conference on Recent Development on Materials, Reliability, Safety and Environmental Issues (IMRSE–2021), Dr. B R Ambedkar NIT Jalandhar, held from 25-27 June, 2021 International
2021 Samarth Agarwal & Rajeevan Chandel Energy Efficient SRAM Design Using FinFETs and Potential Alteration Topology Schemes 10th International Symposium on Embedded Computing and System Design (ISED-2021), DA-IICT, Gandhinagar, Gujarat, 16th -18th July 2021. International
2021 Nivali Yadav, Umesh Thakur, Akanksha Poonia, Rajeevan Chandel Post-Crash Detection and Traffic Analysis 8th IEEE International Conference on Signal Processing and Integrated Networks (SPIN-2021), DoE&CE, ASET, Amity University, Noida, Delhi-NCR, India, 26-27 August 2021 IEEE
2017 Gian Singh, Rajeevan Chandel, and Srishti Marwaha Temperature Aware Dynamic Frequency Scaling Implementation in ARM Core Processor International Conference on Emerging Trends in Engineering Innovations & Technology Management ICET-EITM-17, NIT Hamirpur HP, pp. 446-449, 16-18 Dec 2017 International
2017 Yash Agarwal, Rajeevan Chandel, and Ritu Parekh Performance Evaluation of On-Chip Global Interconnects in DSM Technology using Different Signaling Techniques International Conference on Emerging Trends in Engineering Innovations & Technology Management ICET- EITM-17, NIT Hamirpur HP, pp. 374-380, 16-18 Dec 2017 International
2017 Parmjit Singh, Rajeevan Chandel, and Neha Sharma Stability Analysis of SRAM Cell designed using CNT and GNR Field Effect Transistors IEEE International Conference on Contemporary Computing (IC3), Noida, India, pp. 1-6, 10-12 August, 2017 IEEE
2017 Neha Sharma and Rajeevan Chandel Performance Analysis of SRAM Cell Designed using Floating Gate MOS IEEE International Conference on Inventive Communication and Computing Technologies (ICICCT), Coimbatore, Tamil Nadu, India, pp. 160-165,10-11 March, 2017 IEEE
2021 Bharat K. Jangid, Dilip Singh, Rajeevan Chandel, Ashwani Rana A novel approach for Excitation codebook and Perceptual weighing Filter design. 3rd IEEE International Conference on Innovations in Power & Advanced Computing Technologies (i-PACT2021), Vellore Institute of Technology, Vellore, Tamilnadu, India & University of Malaya (UM), Kuala Lumpur, Malaysia, Paper ID 448, 27-29, November 2021. IEEE
2017 Parmjit Singh and Rajeevan Chandel Design and Performance Analysis of Digital Circuits using Carbon Nanotube IEEE International Conference on Inventive Communication and Computing Technologies, Coimbatore, Tamil Nadu, India, pp. 166-171,10-11 March, 2017. IEEE
2016 Sanjay S. Rajput, Ashish Singh, A.K. Chandel, and Rajeevan Chandel Design of Low-Power High-Gain Operational Amplifier for Bio-Medical Applications IEEE Computer Society Annual International Symposium on VLSI (ISVLSI), Pittsburg, USA, DOI: 10.1109/ISVLSI.2016.62, pp. 355-360, 11-13, July 2016, [DBLP]. IEEE
2016 Ramesh Kumar, Rohit Dhiman, Rajeevan Chandel Performance analysis of Top-contact MLGNR Based Interconnects IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), pp. 11-16, 2016. IEEE
2016 Neha Sharma and Rajeevan Chandel Simulation and Analysis of Low Power Floating Gate MOS Inverter using Tanner EDA ISTE Section Annual Convention (SAC-2016), NIT Hamirpur, HP, India, 30th Sep -2st Oct, 2016. ISTE
2015 Yash Agrawal, Rajeevan Chandel, M. Girish Kumar Performance Analysis of Multilayer Graphene Nano-Ribbon in Current-Mode Signaling Interconnect System IEEE International Symposium on Nanoelectronic and Information Systems (iNIS’15), Indore, India, pp. 297-302, 21-23 Dec 2015. IEEE
2015 Girish Kumar, Rajeevan Chandel, Yash Agrawal Timing and Stability Analysis of Carbon nanotube Interconnects IEEE International Symposium on Nanoelectronic and Information Systems (iNIS’15), Indore, India, pp. 308 – 313, 21-23 Dec 2015. IEEE
2015 Rahul Kumar, Rohit Dhiman, Rajeevan Chandel Low Power, Low Voltage, High Performance Analog Circuits Using FGMOS Transistors-An Overview National ISTE Section Annual Convention, NIT Hamirpur, 30 Sep –1 Oct, 2015. ISTE
2015 Ashish Singh, Rajeevan Chandel Low Dropout Voltage Regulator National ISTE Section Annual Convention, NIT Hamirpur, 30 Sep –1 Oct, 2015. ISTE
2015 Sanjay Singh, Rajeevan Chandel Neural Recording Front End Amplifier Circuitry National ISTE Section Annual Convention, NIT Hamirpur, 30 Sep –1 Oct, 2015. ISTE
2015 Pankaj Sharma, Rajeevan Chandel Vibration-Based Piezoelectric Energy Harvesters along with Power Circuitry -A Review National ISTE Section Annual Convention, NIT Hamirpur, 30 Sep –1 Oct, 2015. ISTE
2015 Rahul Singh, Rohit Dhiman and Rajeevan Chandel Design and Analysis of a Novel Automatic Gain Control Pre-Amplifier Circuit for Hearing Aid Device IEEE International Conference on Electronics, Computing and Communication Technologies, CONECCT-2015, pp. 1-6, Bangalore, July10-11, 2015. IEEE
2015 Ritesh Rampal, Rajeevan Chandel, P. Daniel A Network-on-Chip Router for DeadlockFree Multicast Mesh Routing IEEE International Conference on Electronics, Computing and Communication Technologies, CONECCT-2015, Bangalore, July10-11, 2015. IEEE
2014 Yash Agarwal, Rajeevan Chandel, and Rohit Dhiman High Performance Current mode Receiver Design for On-chip VLSI Interconnects First International Conference on Intelligent Computing & Applications (ICICA-14), Department of Electronics and Communication Engineering, NIT Durgapur, West Bengal 713209 India, December 22-24, 2014. Int. Conf.
2014 Girish Kumar, Rajeevan Chandel, Yash Agrawal CNT and GNR based VLSI Interconnects International Conf. on Emerging Paradigms & Practices in Global Technology, Management & Business Issues; and Review of Business & Technology Research (RBTR), ISSN 1941-9414, vol. 11, no.1, pp. 99-105, published by NIT Hamirpur & MTMI, USA, 22-24 Dec 2014. Int. Conf.
2014 Yash Agrawal, Rajeevan Chandel, M. Girish, Rohit Dhiman Analysis and Estimation of Delay Model in On-chip VLSI Interconnects using Gamma Distribution Function International Conf. on Emerging Paradigms & Practices in Global Technology, Management & Business Issues; and Review of Business & Technology Research (RBTR), ISSN 1941-9414, vol. 11, no.1, pp. 583-588, published by NIT Hamirpur & MTMI, USA, 22-24 Dec 2014. Int. Conf.
2014 Rahul K. Singh, Ritesh, Piyush, Abhishek, Rajeevan Chandel A Modified Low Power Auto-Adaptation Unit for Reconfigurable Analog to Digital Converter in Wireless Applications IEEE International Conference on Parallel, distributed and Grid Computing PDGC-14, Dept of CSE & ICT Jaypee University of Information technology, December 11-13, 2014. IEEE
2014 Sunil Jadav, Munish Vashishth, Rajeevan Chandel Close Form Delay Model For on Chip Signaling with Resistive Load Termination using: Current Mode Technique 9th IEEE International Conference on Industrial and Information Systems (ICIIS), DOI: 10.1109/ICIINFS.2014.7036581, held at ABV-IIITM, Gwalior, pp.1-6, 15-17 Dec 2014. IEEE
2014 Anil Kumar, Rohit Dhiman, Rajeevan Chandel Analysis of crosstalk in SWCNTs bundle and MWCNT interconnects for subthreshold circuits IEEE International Conference on Advanced Communication Control and Computing Technologies (ICACCCT), Ramanathapuram, India DOI: 10.1109/ ICACCCT.2014. 7019304, ISBN No. 978-1-4799-3914-5/14/$31.00 ©2014IEEE, pp. 1273 – 1280, 8-10 May 2014. IEEE
2014 Sonal Shreya & Rajeevan Chandel Performance Analysis of CNTFET Based Digital Logic Circuits Students Conference on Engineering and Systems (SCES), MNNIT Allahabad, DOI: 10.1109/SCES.2014.6880063, pp. 1 – 6, 28-30 May 2014. IEEE
2014 Chandresh Kumar & Rajeevan Chandel Analysis of SRAM Cell Designs for Low Power Applications IEEE International Conference for Convergence of Technology (I2CT), Pune, DOI: 10.1109/I2CT.2014.7092157 , pp. 1 – 4, 6-8 April, 2014. IEEE
2014 Raghvendra P. Varma and Rajeevan Chandel Design and Analysis of Source Coupled Logic Circuits IEEE International Conference for Convergence of Technology I2CT-14, Pune, DOI: 10.1109/I2CT.2014.7092217, pp. 1 – 6, 6-8 April 2014. IEEE
2014 Sonal Shreya and Rajeevan Chandel Design and simulation of energy efficient carbon nanotube based digital circuits 3rd International Conference on Global Technology Initiatives, Rizvi College of Engg, Bandra, 29-30 March 2014. Int.
2014 Yash Agarwal, Rajeevan Chandel, Rohit Dhiman Design and Analysis of Efficient Multilevel Receiver for Current Mode Interconnect System 2nd IEEE International Students' Conference for Electrical, Electronics and Computer Science (SCEECS-2014), at Maulana Azad NIT Bhopal, India, no.349, DOI: 10.1109/SCEECS.2014.6804483, pp. 1 – 6, March 1-2, 2014. IEEE
2014 Rohit Dhiman and Rajeevan Chandel Process variability in sub-threshold VLSI interconnects National Conf. on Advances in Metrology (AdMet–2014), Thapar University, Patiala, February 19–21, 2014. Nat.
2013 Ankit Soni and Rajeevan Chandel Performance Analysis of Bulk Driven MOSFET and CNFET for Low Voltage Applications 4th IEEE Nirma University International Conference on Engineering NUiCONE, pp.1-6, 28-30 Nov 2013. IEEE
2013 Gautam Kumar and Rajeevan Chandel Performance Analysis of Various C-Elements for Asynchronous Logic Design with Process Voltage Variation International Conference on Electrical, Electronics & Computer Science Engineering, ISBN: 978-93-82208-98-3, 23rd June 2013, Dehradun. Int.
2013 Bishwajeet Kumar, Rajeevan Chandel, and Rohit Dhiman Effect of Temperature on Noise in Dynamic CMOS Circuits in Super Threshold Region 3rd National Conference on Recent Advances in Electronics & Communication Technologies RAECT-13 under TEQIP-II & DST New Delhi at GNDE College, Ludhiana, Pb, pp. 13-17, March 21-23, 2013. Nat.
2013 Gargi Khanna, Rajeevan Chandel, and Ashwani K. Chandel Cross-Talk Reduction in Global VLSI Interconnects 3rd National Conference on Recent Advances in Electronics & Communication Technologies RAECT-13 under TEQIP-II & DST New Delhi at GNDE College, Ludhiana, Pb, pp. 158-166, March 21-23, 2013. Nat.
2013 Sonal Shreya, R.P. Varma, Anup, Anil and Rajeevan Chandel Design and Analysis of Semiconductor Devices Using TCAD Tools 3rd National Conference on Recent Advances in Electronics & Communication Technologies RAECT-13 under TEQIP-II & DST New Delhi at GNDE College, Ludhiana, Pb, pp. 59-67, March 21-23, 2013. Nat.

Research Projects



Role Project Type Title Funding Agency From To Amount Status Co-Investigator Sanction Order Sanction Date
Chief Investigator R&D & Manpower Development SMDP-C2SD (Special Manpower Development Project - in Chip to System Design) Project DeitY, MeitY, GoI 25/12/2014 18/08/2020 Rs 94 Lacs On going Dr. Ashwani K. Rana 9(1)/2014-MDD 15/05/2015
Co-Principal Investigator R&D Study and Development of Smart e-System for Crop Protection from Monkeys HIMCOSTE, Shimla (HP) 12/10/2017 12/10/2019 Rs 7 lacs Completed PI Dr. Ashwani K. Rana No. SCSTE/F(8)-1/2016-Vol.-1-3822 12/10/2017
Principal Investigator TAPTEC/ R&D VLSI Thrust Area Project MHRD, GoI 30/03/2000 31/03/2003 Rs 6 Lacs Completed Er. DR Rana No. F.27-1/99-TS-1 Dt 30-03-2000 15/03/2000
Principal Investigator/ Coordinator R&D & Manpower Development SMDP-II project Special Manpower Development Project in VLSI & related softwares DeitY, MeitY, GoI 30/12/2 31/03/2 Rs 50.3 L Completed Dr. Lalit K. Awasthi No. 30/12/2005
Mentor R&D Design of Biometric Attendance System using Fingerprint Technology TEQIP-II 08/10/2013 15/07/2014 50,000/- Completed Ms. Manu Sehgal, Mr.Abhishek Koundal No.NIT/HMR/TE 08/10/2013
Co-Principal Investigator TAPTEC/ Modernization Modernization of Electronics Simulation Lab. MHRD (MoE) 10/04/2000 31/03/2002 5 Lacs Completed Er. D.R. Rana (PI) No. 30/03/2000
Principal Investigator R&D NPMASS Project IISc Bangalore 18/09/2009 31/03/2015 2 Lacs Completed Dr. AK Chandel, Dr. K. Dutta, Dr. G. Khanna NPMASS Project vide No. NIT/H/PS(D)-02/333, dt: 18-9-2009 18/09/2009
Principal Investigator R&D Urban Poverty Alleviation (UPA) Project MUD 01/05/2006 31/03/2009 Rs 1.5 Lacs Completed Dr. S. K. Soni No. 01/05/2006

Research Supervision



Programme Name Scholar Name Research Topic Status Year Co-Suprivisor(s)
Ph.D Er. Gargi Khanna, Reg. No. 2K6-Ph.D.-ECE-30. Investigations on VLSI Interconnects for Performance Enhancement and Mitigation of Non Ideal Effects. Awarded 2012 Dr. Ashwani K. Chandel
Ph.D Er. Sandeep Singh Gill 2K7-PhD-ECE-85 VLSI Circuit Partitioning using Evolutionary Optimization Techniques Awarded 2012 Dr. Ashwani K. Chandel
Ph.D Er. Rohit Dhiman 2K9-PhD-ECE Performance Investigations in VLSI Interconnects for Ultra-Low Power Regime Awarded 2014 -
Ph.D Er. Philemon Daniel 2K8-PhD-ECE-107 Software Based Self-test Techniques for Online Test and Diagnosis of Embedded Controllers and Memories Awarded 2015 -
Ph.D Er. Yash Agarwal 2K13-Ph.D.-E&CE-208 Design, Modeling and Analysis of High Performance VLSI Interconnects Awarded 2016 -
Ph.D Er. Girish M. Kumar 2K13-Ph.D.-E&CE-236 Investigations in CNT and Graphene Interconnects for Deep Submicron Technologies Awarded 2018 -
Ph.D Er. Sunil Jadav, YMCA Univ of S&T, Faridabad, Haryana Modeling and Simulation of Low Power Interconnect Awarded 2018 Dr. Munish Vashishtha
Ph.D Er. Dilip Singh Design, Analysis & FPGA Prototyping of VLSI Modules for Speech Coding Applications On going 2018 -
Ph.D Er. Deepanshu Kaushal Design of Fractal Monopole Antennas for Multiband Applications On going 2018 -
M.Tech Ms. Kanika Nadda Optimal Design of Interconnects using GA Completed 2008 Er. G. Khanna
M.Tech Mr. Harsh Sohal Flash ADC for SoC Applications Completed 2008 -
M.Tech Mr. Ashwani Kr Sanwal Investigations on Low Power Techniques on CMOS Circuits Completed 2008 -
M.Tech Ms. Rakhi Puri Optimal Design of Adder Circuits Completed 2008 -
M.Tech Mr. Y. Nataraj ASIC Prototyping of DTV Input Processing Engine Completed 2008 Er. Robert KA, ST Microelectronics
M.Tech Ms. Preeti Sharma Investigations on Repeaters & Buffers for Interconnects Completed 2008 Er. G. Khanna
M.Tech Mr. Ankush Chunn Performance analysis of Sample and hold circuits for VLSI applications Completed 2009 -
M.Tech Mr. Praveen Kumar V Investigations on Low power CMOS Adders & Multipliers Completed 2009 -
M.Tech Ms. Neha Agarwal Implementation and study of various dynamic logic circuits Completed 2009 -
M.Tech Mr. Sudhakar Singh Chauhan Design and Performance Analysis of Low Power High Speed Flash ADC Completed 2009 Dr. SC Bose, CEERI Pilani
M.Tech Mr. Surya Naik Ultra low Power Standard Cell Library design Completed 2009 -
M.Tech Mr. Kiran Kr. Chadda Design & Analysis of Low Power CMOS Adders and Multipliers Completed 2010 -
M.Tech Mr. Ashutosh Nandi Design and analysis of low power high performance digital adders with on-chip testing feasibility Completed 2010 Er. P. Daniel
M.Tech Mr. Sandeep Sharma Modeling and Analysis of Performance Parameters of Different Interconnects for VLSI circuits Completed 2010 -
M.Tech Ms. Viveka Paliwal Noise Tolerance Improvement Techniques for High Performance Dynamic Circuits Completed 2010 -
M.Tech Mr. Rajneesh Sharma Design and analysis of Threshold Inverter Quantization based Flash Analog to Digital Converter Completed 2010 Er. G. Kumar
M.Tech Ms. Purnima Sharma (09M419) Noise Tolerance Improvement Techniques for Dynamic Circuits in Super and Sub-Threshold Regimes Completed 2011 -
M.Tech Mr. Atul kumar Nishad (09M401) Design and Analysis of Low Power Hybrid CMOS and GDI Technique VLSI Circuits Completed 2011 -
M.Tech Mr. Dhrub Solanki (09M414) Design and Analysis of Low Power VCO for VLSI and Communication Systems Completed 2011 -
M.Tech Mr. Tafseer Alam (09M411) Modelling and Analysis of CNT Interconnects for high Performance VLSI applications Completed 2011 -
M.Tech Mr. Ravi Goel (10M401) Design and Analysis of Ultra Low Power SRAM Cache Memory Cell Completed 2012 -
M.Tech Mr. Dhirender Kumar (10M414) PVT Analysis of Ultra-Low Power Digital Subthreshold Logic Circuits Completed 2012 -
M.Tech Mr. Sudershan Neekhra (10M417) IDDQ Testing in Deep Submicron Region Completed 2012 -
M.Tech Mr. Chandan Jha (11M406) Power and Throughput Centric Design of Digital VLSI Circuits using Pipelining Technique Completed 2013 -
M.Tech Mr. Gautam Kumar (11M412) Power, Delay and Area Efficient Asynchronous Logic Design Completed 2013 -
M.Tech Mr. Bishwajeet (11M403) Design Techniques for Improvement of Noise Tolerance in VLSI Dynamic Circuits for Ultra Low Power Applications Completed 2013 -
M.Tech Ms. Sonal Shreya (12M439) Design and analysis of digital circuits using carbon nano-material based transistor for multivalued logic Completed 2014 -
M.Tech Mr. Raghvandra P. Singh (12M439) Source Coupled Logic Circuits Completed 2014 -
M.Tech Mr. Chandresh K. Sharma (12M439) Design & Analysis of SRAM Cells for Low Power Applications Completed 2014 -
M.Tech Mr. Rahul Kumar Singh (13M408) Analog Front End Design of Hearing Aid Device Completed 2015 -
M.Tech Mr. Ritesh Rampal (13M410) Design and Implementation of Network-on-Chip based Interconnection Network for Neuromorphic Systems Completed 2015 -
M.Tech Mr. Rohit Agarwal 13M404 Performance Evaluation of Carbon Nano Tube (CNT) Interconnects Completed 2015 Dr. Rohit Dhiman
M.Tech Mr. Sanjay Singh Rajput (14M409) Front-End Amplifier for Bio-Medical Signal Acquisition Completed 2016 -
M.Tech Mr. Pankaj Sharma (14M416) Design of Vibrational based piezoelectric Energy Harvester for powering wireless sensor nodes Completed 2016 -
M.Tech Mr. Ashish Singh (14M417) Full On-Chip CMOS Low Dropout Voltage Regulator Design and Analysis Completed 2016 -
M.Tech Ms. Neha Sharma (15M401) Design and Analysis of Low Power SRAM Architectures using CMOS and Floating Gate MOS Technologies Completed 2017 -
M.Tech Mr. Parmjit Singh (15M402) Design and Performance Analysis of Digital Circuits using Carbon Nanotube Transistors Completed 2017 -
M.Tech Ms. Sakshi Goel (16M401) Design, Analysis and Estimation of Line Spectral Frequencies for Speech Encoder and Decoder Completed 2018 -
M.Tech Mr. Dilip Singh (16M407) Hardware Design and Implementation of CELP Based Speech Vocoder Completed 2018 -
M.Tech Mr. Ankit Kumar Maurya (17M401) Characterization of SRAM Tile of size 32x32 with Access Time Constraint Completed 2019 -
M.Tech Mr. Bharat Kumar Jangid (17M410) Implementation of Stochastic and Adaptive Modules for Vocoder Design Completed 2019 -
M.Tech Mr. Animesh Shrivastava (15MI445) Performance Enhancement in VLSI Circuits using Quantum Cellular Automata Design Completed 2020 -
M.Tech Mr. Kommukuri Madhu Kiran (18M405) Design and Analysis of SRAM Tiles Using Lector Technique For Low Power Applications Completed 2020 -
M.Tech Mr. Pawan Kumar Pandey (18M412) Hardware Design of Low Power Linear Prediction Coder for Speech Application Completed 2020 -
M.Tech Mr. Dasari Nagasai Nagarjuna (15MI437) Implementation of Zero-Input Zero-State Method For Codebook Search In CELP Based Vocoder Using Vivado HLS Completed 2020 -
M.Tech Mr. Vollite Bhargav (15MI453) Design and Implementation of Various Modules in Advanced High-performance Bus (AHB)-Lite Completed 2020 -
M.Tech Ms. Sonalika Singh (19M401) Design and Analysis of Low Noise Amplifier using Active Inductor for 100nm CMOS Technology Completed 2021 -
M.Tech Mr. Baisen Razda (19M419) Machine Learning Usage Analysis for Decision Making in Automobile Sector Completed 2021 -
M.Tech Ms. Afreen Haider (16MI434) Design and Analysis of a Single Stage Differential Amplifiers using MOSFETs and FINFETs Completed 2021 -
M.Tech Mr. Samarth Agarwal (16MI448) Design and Analysis of SRAM using CMOS, FinFETs and Gallium Nitride Field Effect Transistors Completed 2021 My 50th PG Student

Patents



Title Reg./Ref.No. Date of Award/Filling Awarding Agencies Status

Teaching Experience



Position Held Department and Organization From To Total Experience
2. Associate Professor E&CE Department, NIT Hamirpur HP 01/07/2006 18/10/2013 7yr, 3m & 17d
3. Assistant Professor E&CE Department, NIT Hamirpur HP 12/09/2005 30/06/2006 9m & 19d
4. Selection Grade Lect. E&CE Department, NIT Hamirpur HP 01/07/2003 11/09/2005 2yr, 2m & 10d
5. Senior- Lecturer E&CE Department, NIT Hamirpur HP 27/12/1997 30/06/2003 5yr, 6m & 4d
6. Lecturer E&CE Department, REC Hamirpur HP (now NIT Hamirpur HP) 17/08/1991 26/12/1997 6yr, 4m & 9d
7. Lecturer Ad-hoc E&CE Department, REC Hamirpur HP (now NIT Hamirpur HP) 01/08/1990 31/05/1991 10m
1. Professor E&CE Department, NIT Hamirpur HP 19/10/2013 8yr, 4m, 12d

Administrative Experience



Position Held Department and Organization From To
Head of Department E&CE, National Institute of Technology Hamirpur HP 27/07/2006 03/08/2009
Head of Department E&CE, National Institute of Technology Hamirpur HP 29/08/2012 15/10/2014
DEAN (Research & Consultancy) National Institute of Technology Hamirpur (HP) 03/10/2016 27/09/2019
Editor Institute Newsletter & Brochure National Institute of Technology Hamirpur (HP) 16/05/2011 16/10/2012
Convener Women Cell National Institute of Technology Hamirpur (HP) 26/07/2007 29/11/2012
Coordinator Centre for Continuing Education National Institute of Technology Hamirpur (HP) 17/07/2009 16/10/2012
Member Editorial Board Newsletter National Institute of Technology Hamirpur (HP) 28/12/2012 29/12/2015
Warden, PGH National Institute of Technology Hamirpur (HP) 21/09/1999 06/06/2002
Member of Selection Committees for Faculty & Staff 2006 onwards National Institute of Technology Hamirpur (HP) 14/05/2007
Resident Warden, PGH REC Hamirpur HP (now NIT Hamirpur HP) 10/08/1990 14/08/1992
Chairperson DPGC & DUGC, E&CED E&CED, NIT Hamirpur (HP) 15/08/2006 03/07/2009
Coordinator NBA Accreditation of E&CED E&CED, NIT Hamirpur (HP) 09/10/2009 30/08/2012
Convener DPGC & DUGC E&CED May to Sep 2006 & Chairperson thereafter E&CED, NIT Hamirpur (HP) 01/09/2006 03/09/2009
Chairperson DPGC & DUGC, E&CED E&CED, NIT Hamirpur (HP) 30/08/2012 15/10/2014
DEAN (Academic) National Institute of Technology Hamirpur (HP) 17/07/2020 31/05/2021
Convener DDPC, E&CED E&CED, NIT Hamirpur (HP) 01/09/2019 31/07/2020
Member DDPC, DoCSE NIT Hamirpur HP 01/11/2018 31/12/2021
Member DMPC, DoECE NIT Hamirpur HP 01/12/2021
Member DMPC, DoCSE NIT Hamirpur HP 03/01/2022

Book/Chapters Written



Type Title Publisher Author(s) ISBN/ISSN No. Year
Book Compact Models and Performance Investigations for Subthreshold Interconnects. Series: Energy Systems in Electrical Engineering, Rohit Dhiman and Rajeevan Chandel, Compact Models and Performance Investigations for Subthreshold Interconnects. Series: Energy Systems in Electrical Engineering, XIII, 113 p. 45 illus. Springer Rohit Dhiman and Rajeevan Chandel ISBN 978-81-322-2132-6 2015
Book Chapter High Performance Current mode Receiver Design for On-chip VLSI Interconnects. Chapter 54 in Springer Series: Advances in Intelligent Systems and Computing, vol. 343, pp. 527-536 Springer Yash Agarwal, Rajeevan Chandel, and Rohit Dhiman. ISBN 978-81-322-2267-5 2014
Book Chapter Stability analysis of carbon nanotube interconnects. In Book Series: Advances in Intelligent Systems and Computing. Springer M. Girish Kumar, Y. Agrawal and Rajeevan Chandel. 978-81-322-2268-2_54 2016
Book Chapter Time-domain analytical modeling of current-mode signaling bundled single-wall carbon nanotube interconnects. In Book Series: Advances in Intelligent Systems and Computing Springer Y. Agrawal, M. Girish, and Rajeevan Chandel DOI: 10.1007 2016
Book Chapter Performance Analysis of Current-Mode Interconnect System in Presence of Process, Voltage, and Temperature Variations. In Book: Garg A., Bhoi A., Sanjeevi kumar P., Kamani K. (Eds) Advances in Power Systems and Energy Management. Lecture Notes in Electrical Engineering, vol. 436, pp. 543-551 Springer, Singapore Yash Agrawal, Rutu Parekh, Rajeevan Chandel. ISBN 978-981-10-4393-2 2018
Book Chapter CNT and GNR based VLSI Interconnects, in book: Review of Business & Technology Research (RBTR), vol. 11, no.1, pp. 99-105 Review of Business & Technology Research (RBTR) Girish Kumar, Rajeevan Chandel, Yash Agrawal ISSN 1941-9414 2014
Book Chapter Analysis and Estimation of Delay Model in On-chip VLSI Interconnects using Gamma Distribution Function, in Book Review of Business & Technology Research (RBTR), vol. 11, no.1, pp. 583-588, NIT Hamirpur & MTMI, USA. Review of Business & Technology Research (RBTR) Yash Agrawal, Rajeevan Chandel, M. Girish, Rohit Dhiman. ISSN 1941-9414 2014
Book Chapter Impact of Parameter Variability on Delay and Power Dissipation in Dielectric Inserted MLGNR Interconnects, in Book Proceedings of International Conference on Emerging Trends in Engineering Innovations & Technology Management, EED, NIT Hamirpur HP, pp. 381-385. Excel India Publishers Rajeevan Chandel and M. Girish Kumar ISBN: 978-93-86724-31-1 2017
Book Chapter Voltage Scaled Repeaters for Low-Power Long Interconnections in VLSI Circuits, in Book titled Progress in VLSI Design and Test 2004, Edited by Dr. CP Ravikumar. Elite Publishing House Pvt. Ltd Rajeevan Chandel, S Sarkar and RP Agarwal ISBN: 81-8890 2004
Book Chapter Repeater Design Considerations for VLSI Interconnects in Book titled Progress in VLSI Design and Test, Edited by Dr. CP Ravikumar. Phoenix Publishing House Pvt Ltd Kumar Vijay Mishra and Rajeevan Chandel ISBN: 81-7484-049-4 2002
Book Chapter Reliability Issues in VLSI Design and Technology, in Book titled Frontiers of VLSI Design and Test Edited by Dr. CP Ravikumar. Phoenix Publishing House Pvt Ltd Rajeevan Chandel ISBN:81-7484-061-3 2001
BOOK VLSI and Post-CMOS Electronics- Design, Modelling and Simulation (Vol. 1) IET, Stevenage, England (UK) Rohit Dhiman, Rajeevan Chandel, (Editors) ISBN: 978-1-83953-051-7 2019
Book Chapter Energy Efficient SRAM Design Using FinFETs and Potential Alteration Topology Schemes, in Artificial Intelligence Driven Circuits and Systems, Mishra B., Mathew J., Patra P. (Eds). Lecture Notes in Electrical Engineering Springer, Singapore Samarth Agarwal, Rajeevan Chandel ISSN: 1876-1119 2022

Expert Talks



Title Place Year Description of Event
VLSI Design - Case Studies & Emerging Issues Gwalior, Madhya Pradesh 2021 Keynote Plenary Lecture delivered on 12th July 2021 by Prof. Rajeevan Chandel in AICTE Sponsored Short Term Training Program (STTP) on “Emerging Issues of VLSI Design” organized by ITM University Gwalior, Madhya Pradesh, held from 12th to 17th July 2021
CMOS VLSI Design - Case Studies & Research Avenues NIT Hamirpur, H.P. 2021 Expert Lecture delivered by Prof. R. Chandel on 2nd June 2021, in the ATAL FDP Sponsored by AICTE Training and Learning (ATAL) Academy on “Recent Advances and Challenges in Nanoscale Devices: Design, Materials, and Applications Perspective” held from 1st to 5th June 2021, E&CE Dept., NIT Hamirpur, H.P.
VLSI Design Challenges and Solutions Dr. B.R. Ambedkar NIT Jalandhar 2021 Expert lecture delivered by Prof. R. Chandel on 14th Jan 2021 in the STC on Recent Challenges in IC and Applications organized by Dr. B.R. Ambedkar NIT Jalandhar from 11th to 15th Jan 2021
MOS Modeling Dr. B.R. Ambedkar NIT Jalandhar 2020 Expert Lecture delivered by Prof. RChandel on 20th August, 2020 in the Short Term Course on Sub-micrometer Semiconductor Device to Circuit Co-Design and Modelling Techniques, organized by Department of the Electronics and Communication Engineering, Dr. B.R. Ambedkar NIT Jalandhar, sponsored by TEQIP-III, during 20th to 24th August 2020
VLSI Signal Processing- From a Designer’s Perspective Dr. B.R. Ambedkar NIT Jalandhar 2020 Dr. Rajeevan Chandel delivered a Planery Lecture (online on 23rd July 2020) in 1st International Conference on Communication, Computing and Signal Processing (CCSP-2020), organized by Dr. B.R. Ambedkar NIT Jalandhar, held during 23-24 July, 2020
VLSI Design RTU, Rajasthan 2020 Dr. Rajeevan Chandel delivered an Expert Invited Lecture in the International Webinar, organized by Poornima College of Engg, RTU, Rajasthan, on 8th June 2020.
An Insight into VLSI Trends & MOS Modeling Gwalior, Madhya Pradesh 2021 Keynote plenary Lecture delivered on 26th Nov 2021 by Prof. Rajeevan Chandel in AICTE Sponsored Short Term Training Program (STTP) on “Emerging Issues of VLSI Design” organized by ITM University Gwalior, Madhya Pradesh, held from 21st Nov to 26th Nov, 2021.
National Education Policy-2020 (NEP-2020) in Engineering Education – Reforms, Impact & Some Case Studies Poornima College of Engineering, Jaipur (Rajasthan) 2021 Prof. Rajeevan Chandel delivered an Expert Lecture on 23rd December 2021, in the AICTE-ISTE sponsored e-Induction
Research Opportunities in VLSI Design NIT Hamirpur HP 2021 Keynote Lecture delivered by Prof. R. Chandel on 11th Jan 2022 in the five-day Online Workshop on “Intelligent Device Computing, Communication and Signal Processing” held from January 10-14, 2022, DoECE, NIT Hamirpur HP.
Electronics & Communication Engineering in Industry 4.0 MRU, Faridabad, Haryana 2022 Prof. Rajeevan Chandel delivered a Keynote address on 4th Feb 2022 in the International Conference on “Robotics, Automation & Communication Engineering for Industry 4.0” (ICRACEI4.0) on February 4th & 5th, 2022, organized by Manav Rachna University, Faridabad, Haryana.

Consultancy



Title of Consultancy Client Organization Faculty Involved Amount(INR) Status

International and National Exposure



Sr.No. Title Description
1 IIT Delhi Attended STCs; Alumnus
2 IIT Roorkee Participation in STCs; Expert in STCs; Alumnus
3 DeitY, MeitY, New Delhi Collaboration in SMDP Projects, Sponsorship for IPR National Seminar
4 IIT Kanpur Participation in workshops
5 IIT Bombay Participation in Project meetings, workshops
6 IISc Bangalore Participation in Workshops
7 NIT Kurukshetra, NIT Jalandhar, MNNIT Jaipur Expert for Ph.D. & M.Tech. defense Oral Boards, Resource Person in STCs
8 ESCI, Hyderabad Participation in STTP
9 IIT Mandi, HP Visiting Faculty (for Semester long Course)
10 IIT Rupnagar, Ropar, Pb Academic & research collaboration
11 Wipro, Bangalore, Karnataka Participation in Conference
12 GNDE College, Ludhiana, Pb Advisory committee member & Key-Note speaker for series of Conferences, Subject Expert BOS, Resource person in STCs
13 CEERI-CSIR Pilani, Rajasthan Academic and Research collaborations through SMDP projects, attended VLSI Technology training
14 NITTR Chandigarh; PEC, Chandigarh; UIET, PU, Chandigarh Academic collaboration, Resource Person in STCs, Expert for Ph.D. & M.Tech. defense Oral Boards
15 TIET (now Thapar University), Patiala, Pb Expert for PG Thesis defense Oral Boards; Alumnus
16 HIPA, Shimla, HP Participation in STTP
17 HPTU, Hamirpur, HP; HP University, Shimla BOS Subject Expert, Expert for Faculty interviews, Expert for Affiliation of various Institutes
18 CSIO-CSIR Chandigarh, NPL-CSIR New Delhi Academic and Research collaboration

Conferences/Courses Organized



Category Type Title Venue From To Designation
fdp Summer School cum Training Programme under TEQIP VLSI Design & Optimization Techniques (VDOT 2006) E&CED, NIT Hamirpur HP 05/06/2006 09/06/2006 Coordinator
workshop Workshop under Community Service, TEQIP Operation & Application of Electronics Test & Measuring Equipment E&CED, NIT Hamirpur HP 01/11/2006 02/11/2006 Coordinator
fdp Winter School cum Training Programme under TEQIP VLSI Design & Recent Trends in Nano-Electronics (VDNE 2006) E&CED, NIT Hamirpur HP 18/12/2006 22/12/2006 Coordinator
conference NATIONAL CONFERENCE (Under TEQIP, VSI, SMDP-II) Design Techniques for modern electronic devices, VLSI & Communication systems DTVC-2007 E&CED, NIT Hamirpur HP 14/05/2007 15/05/2007 GENERAL CHAIR cum Coordinator
stc Short Term Course cum Training Programme HDL & VLSI EDA Tools E&CED, NIT Hamirpur HP 21/05/2007 25/05/2007 Chief-Coordinator
stc Short Term Course cum Training Programme under UPA Project Repair & Maintenance of Electronic & Electrical gadgets E&CED, NIT Hamirpur HP 11/06/2007 15/06/2007 Coordinator
stc STC under TEQIP Services to Community Use of Multimedia and Electronic Equipment E&CED, NIT Hamirpur HP 27/09/2007 01/10/2007 Coordinator
stc STTP under NIT Hamirpur Seminar & SMDP-II Project VLSI Design & Tools VLSI-07 E&CED, NIT Hamirpur HP 04/12/2007 08/12/2007 Chief-Coordinator
stc STC under UPA Project Safe Use & Maintenance (Operation & Repair) of Electronics & Electrical Gadgets E&CED, NIT Hamirpur HP 07/04/2008 11/04/2008 Coordinator
workshop National Workshop VLSI & Communication Systems VCS-08 E&CED, NIT Hamirpur HP 05/06/2008 06/06/2008 Coordinator
stc STC EDA Tools for Electronic System Design ETESD-2018 E&CED, NIT Hamirpur 01/01/2018 06/01/2018 Coordinator
workshop Evaluation Workshop of SMDP-C2SD project VLSI Lab and Seminar Hall of E&CED. A team of Five Experts headed by Dr. SC Bose and Dr. Abhijit Karmakar from CEERI Pilani, Rajasthan visited NIT Hamirpur for the same. E&CED, NIT Hamirpur HP 04/05/2018 04/05/2018 Coordinator

Profile Summary

Last Update: 13/03/2022 03:30am
Logo
Name : Prof. (Mrs.) Rajeevan Chandel
Designation : Professor
Department : Electronics & Communication Engineering
Qualification : Ph.D. (IIT Roorkee), M.Tech. (IIT Delhi), B.E. (TIET, Patiala)
Phone : 254624
Email ID : rchandel@nith.ac.in
Profile URL : https://portfolios.nith.ac.in/index.php?/nith/dr-mrs-rajeevan-chandel-
Date of Birth : 11/27/1968
Date of Joining : 08/17/1991

Specialization

Low Power VLSI Design, Modeling & Simulation

Education Qualification


Name of the Degree Year of Passing Institute/University
1. Matriculation (ICSE Board) 1984 Sacred Heart High School Sidhpur, Dharamshala, Himachal Pradesh
2. Pre-University Class 1985 DAV College, Kangra, HP University
3. Pre-Engineering 1986 DAV College, Kangra, HP University
4. B.E. (Electronics and Communication Engineering) 1990 Thapar Institute of Engineering & Technology (now Thapar University), Patiala, Pb
5. M.Tech. (Integrated Electronics & Circuits) 1997 Indian Institute of Technology (IIT), Delhi
6. Ph.D. (Low-Power VLSI Design) 2005 Indian Institute of Technology (IIT), Roorkee

Teaching Experience


Programme Name Department And Organization From To Total Experience
2. Associate Professor E&CE Department, NIT Hamirpur HP 01/07/2006 18/10/2013 7yr, 3m & 17d
3. Assistant Professor E&CE Department, NIT Hamirpur HP 12/09/2005 30/06/2006 9m & 19d
4. Selection Grade Lect. E&CE Department, NIT Hamirpur HP 01/07/2003 11/09/2005 2yr, 2m & 10d
5. Senior- Lecturer E&CE Department, NIT Hamirpur HP 27/12/1997 30/06/2003 5yr, 6m & 4d
6. Lecturer E&CE Department, REC Hamirpur HP (now NIT Hamirpur HP) 17/08/1991 26/12/1997 6yr, 4m & 9d
7. Lecturer Ad-hoc E&CE Department, REC Hamirpur HP (now NIT Hamirpur HP) 01/08/1990 31/05/1991 10m
1. Professor E&CE Department, NIT Hamirpur HP 19/10/2013 8yr, 4m, 12d

Administrative Experience


Position Held Department And Organization From To
Head of Department E&CE, National Institute of Technology Hamirpur HP 27/07/2006 03/08/2009
Head of Department E&CE, National Institute of Technology Hamirpur HP 29/08/2012 15/10/2014
DEAN (Research & Consultancy) National Institute of Technology Hamirpur (HP) 03/10/2016 27/09/2019
Editor Institute Newsletter & Brochure National Institute of Technology Hamirpur (HP) 16/05/2011 16/10/2012
Convener Women Cell National Institute of Technology Hamirpur (HP) 26/07/2007 29/11/2012
Coordinator Centre for Continuing Education National Institute of Technology Hamirpur (HP) 17/07/2009 16/10/2012
Member Editorial Board Newsletter National Institute of Technology Hamirpur (HP) 28/12/2012 29/12/2015
Warden, PGH National Institute of Technology Hamirpur (HP) 21/09/1999 06/06/2002
Member of Selection Committees for Faculty & Staff 2006 onwards National Institute of Technology Hamirpur (HP) 14/05/2007
Resident Warden, PGH REC Hamirpur HP (now NIT Hamirpur HP) 10/08/1990 14/08/1992
Chairperson DPGC & DUGC, E&CED E&CED, NIT Hamirpur (HP) 15/08/2006 03/07/2009
Coordinator NBA Accreditation of E&CED E&CED, NIT Hamirpur (HP) 09/10/2009 30/08/2012
Convener DPGC & DUGC E&CED May to Sep 2006 & Chairperson thereafter E&CED, NIT Hamirpur (HP) 01/09/2006 03/09/2009
Chairperson DPGC & DUGC, E&CED E&CED, NIT Hamirpur (HP) 30/08/2012 15/10/2014
DEAN (Academic) National Institute of Technology Hamirpur (HP) 17/07/2020 31/05/2021
Convener DDPC, E&CED E&CED, NIT Hamirpur (HP) 01/09/2019 31/07/2020
Member DDPC, DoCSE NIT Hamirpur HP 01/11/2018 31/12/2021
Member DMPC, DoECE NIT Hamirpur HP 01/12/2021
Member DMPC, DoCSE NIT Hamirpur HP 03/01/2022

Research Experience

Research Interests : Low-Power VLSI Design, VLSI Interconnect Design, Nano-electronics, MEMS, Electronic Device Modeling and Simulation
Brief Research Statement : Dedicated towards students, academic fraternity, society and community, my vision is to see India excel in all areas of VLSI Design, Electronics and Communication Engineering. Low Power CMOS VLSI Design is my core research area. The various aspects of modeling and simulation of VLSI interconnects, devices & circuits, and ASIC design are the other major areas of my research work.

Research Projects


Role Project Type Title Funding Agency From To Amount Status Co-Investigator Sanction OrderSanction Date
Chief Investigator R&D & Manpower Development SMDP-C2SD (Special Manpower Development Project - in Chip to System Design) Project DeitY, MeitY, GoI 25/12/2014 18/08/2020 Rs 94 Lacs On going Dr. Ashwani K. Rana 9(1)/2014-MDD 15/05/2015
Co-Principal Investigator R&D Study and Development of Smart e-System for Crop Protection from Monkeys HIMCOSTE, Shimla (HP) 12/10/2017 12/10/2019 Rs 7 lacs Completed PI Dr. Ashwani K. Rana No. SCSTE/F(8)-1/2016-Vol.-1-3822 12/10/2017
Principal Investigator TAPTEC/ R&D VLSI Thrust Area Project MHRD, GoI 30/03/2000 31/03/2003 Rs 6 Lacs Completed Er. DR Rana No. F.27-1/99-TS-1 Dt 30-03-2000 15/03/2000
Principal Investigator/ Coordinator R&D & Manpower Development SMDP-II project Special Manpower Development Project in VLSI & related softwares DeitY, MeitY, GoI 30/12/2 31/03/2 Rs 50.3 L Completed Dr. Lalit K. Awasthi No. 30/12/2005
Mentor R&D Design of Biometric Attendance System using Fingerprint Technology TEQIP-II 08/10/2013 15/07/2014 50,000/- Completed Ms. Manu Sehgal, Mr.Abhishek Koundal No.NIT/HMR/TE 08/10/2013
Co-Principal Investigator TAPTEC/ Modernization Modernization of Electronics Simulation Lab. MHRD (MoE) 10/04/2000 31/03/2002 5 Lacs Completed Er. D.R. Rana (PI) No. 30/03/2000
Principal Investigator R&D NPMASS Project IISc Bangalore 18/09/2009 31/03/2015 2 Lacs Completed Dr. AK Chandel, Dr. K. Dutta, Dr. G. Khanna NPMASS Project vide No. NIT/H/PS(D)-02/333, dt: 18-9-2009 18/09/2009
Principal Investigator R&D Urban Poverty Alleviation (UPA) Project MUD 01/05/2006 31/03/2009 Rs 1.5 Lacs Completed Dr. S. K. Soni No. 01/05/2006

Journal Publications


Year Author(s) Journal Name Title & Vol. No. Indexing (SCI/Web of science/Scopus)
2005 Rajeevan Chandel, S. Sarkar and R.P. Agarwal IETE Journal of Research, Taylor & Francis Performance Controlling Parameters of Voltage-Scaled Repeaters for Long Interconnections, vol. 51, no. 2, pp. 107-113 SCIE
2005 Rajeevan Chandel, S. Sarkar and R.P. Agarwal Microelectronics International, Emerald, UK. Transition Time Considerations in Voltage-Scaled Repeaters, vol. 22, no. 3, pp.39-40 SCI
2000 Rajeevan Chandel and Ashwani Kumar IETE Journal of Research Taylor & Francis Design and Development of Dielectric based Electrostatic Microactuators, vol.46, no. 4, pp. 261-264 SCIE
2005 Rajeevan Chandel, S. Sarkar and R.P. Agarwal Microelectronics International, Emerald, UK. Delay Analysis of a Single Voltage-Scaled-Repeater driven Long Interconnect, vol. 22, no. 3, pp. 28-33 SCI
2005 Rajeevan Chandel, S. Sarkar and R.P. Agarwal Microelectronics International, Emerald Pub. UK. Repeater insertion in global interconnects in VLSI circuits, vol. 22, no. 1, pp. 43-50 SCI
2006 Rajeevan Chandel, S. Sarkar and R.P. Agarwal Microelectronics International, Emerald UK. Repeater stage timing analysis for VLSI resistive interconnects, vol. 23, no. 3, pp. 19-25 SCI
2007 Rajeevan Chandel, S. Sarkar and R.P. Agarwal Microelectronics Journal, Elsevier Science An Analysis of Interconnect Delay Minimization by Low-Voltage Repeater Insertion, vol. 38, no. 4-5, pp 649-655 SCI
2007 Rajeevan Chandel, S. Sarkar, and Ashwani K. Chandel Journal of Low Power Electronics, ASP, USA. Investigations on Short-Circuit Power Dissipation in Repeater Loaded VLSI Interconnects, vol. 3, no. 3, pp. 337–344 Scopus
2007 Rajeevan Chandel, S. Sarkar and R.P. Agarwal International Journal of Modelling & Simulation, Taylor & Francis. Delay and Power Management of Voltage-Scaled Repeaters for Long Interconnects, vol. 27, no. 4, pp. 333-339 Scopus
2008 Rajeevan Chandel, Y. Nataraj, G. Khanna Journal of Nanoelectronics & Optoelectronics (JNO), ASP, USA Performance Analysis of Voltage-Scaled Static and Dynamic CMOS Circuits, vol.3, no.2, pp. 171-176 SCI
2009 Gargi Khanna, Rajeevan Chandel, Ashwani K. Chandel, S. Sarkar Microelectronics International, Emerald UK. Analysis of non-ideal effects in coupled VLSI interconnects with active and passive load variation, vol. 26, no. 1, pp. 3-9 SCI
2010 Ashutosh Nandi, Rajeevan Chandel Journal of Low Power Electronics, ASP, USA Design and Analysis of Sub-DT Sub-Domino Logic Circuits for Ultra Low Power Applications, vol. 6, No. 4, pp. 513-520 Scopus
2010 Kiran K. Chaddha, Rajeevan Chandel Journal of Low Power Electronics, ASP, USA Design and Analysis of a Modified Low Power CMOS Full Adder Using Gate-Diffusion Input Technique, vol. 6, No. 4, pp. 482-490 Scopus
2011 Sandeep Singh Gill, Rajeevan Chandel, Ashwani K. Chandel Journal of Shanghai Jiaotong Univ. (Science), Elsevier Efficient Clustering and Simulated Annealing Approach for Circuit Partitioning, vol.16, No. 6, pp. 708-712 Scopus
2012 Rohit Dhiman, Rajeevan Chandel International Journal of Modelling and Simulation, Taylor & Francis. Delay Analysis of a CMOS Buffer Driven RLC Interconnect Load for Sub-Threshold Applications, vol. 32, no.1, pp. 18-23 Scopus
2012 Rohit Dhiman, Rajeevan Chandel Journal of Low Power Electronics, ASP, USA Sub-Threshold Delay and Power Analysis of CMOS Buffer Driven Interconnect Load for Ultra Low Power Applications, vol. 8, no. 1, pp. 39-46 Scopus
2014 Rohit Dhiman, Rajeevan Chandel Journal of Computational Electronics, Springer. Crosstalk analysis of CMOS buffer driven interconnects for ultra-low power applications, vol. 13, no. 2, pp. 360-369 SCI
2015 Rohit Dhiman and Rajeevan Chandel Circuits, Systems and Signal Processing, Springer, USA. Dynamic crosstalk analysis in coupled interconnects for ultra-low power applications, vol. 34, no. 1, pp. 21–40 SCI
2015 Rohit Dhiman, Rohit Sharma and Rajeevan Chandel Analog Integrated Circuits & Signal Processing, Springer, USA. Compact models and delay computation of sub-threshold interconnect circuits, vol. 84, no.1, pp. 53-65 SCI
2015 Sunil Jadav, Munish Vashistah, Rajeevan Chandel International Journal of Modelling and Simulation, Taylor & Francis, RLC equivalent RC delay model for global VLSI interconnect in current mode signalling, vol. 35, no. 1, pp. 27–34 Scopus
2015 Rohit Dhiman and Rajeevan Chandel Analog Integrated Circuits & Signal Processing, Springer , USA. Compact models and computation of crosstalk for sub-threshold interconnect circuits, vol. 82, no.3, pp. 637–652 SCI
2016 Yash Agrawal and Rajeevan Chandel IETE Technical Review, Taylor & Francis. **(IETE- KS KRISHNAN MEMORIAL AWARD (2017) Awarded to Yash Agrawal & Dr. Rajeevan Chandel for Best System Oriented Paper) Crosstalk Analysis of Current-Mode Signalling-Coupled RLC Interconnects Using FDTD Technique**, vol. 33, no. 2, pp. 148-159 SCIE
2017 Yash Agrawal, M. Girish Kumar and Rajeevan Chandel IEEE Transactions on Electromagnetic Compatibility. A Novel Unified Model for Copper and MLGNR Interconnects Using Voltage- and Current-Mode Signaling Schemes, vol. 59, no. 1, pp. 217-227 SCI
2017 M. Girish Kumar, Y. Agrawal, and Rajeevan Chandel IET Circuits, Devices and Systems Modelling and Performance Analysis of Dielectric Inserted Side Contact Multilayer Graphene Nanoribbon Interconnects, vol. 11, no. 3, pp. 232-240, May 2017 SCI
2018 M. Girish Kumar, Rajeevan Chandel, and Y. Agrawal IEEE Transactions on Electromagnetic Compatibility An Efficient Crosstalk Model for Coupled Multi-Walled Carbon Nanotube Interconnects, vol. 60, no. 2, pp. 487 – 496 SCI
2018 Yash Agrawal, M. G. Kumar, and Rajeevan Chandel Circuits, Systems, and Signal Processing, Springer A Unified Delay, Power and Crosstalk Model for Current Mode Signaling Multiwall Carbon Nanotube Interconnects,” Paper SCIE
2018 Yash Agrawal, M. Girish, and Rajeevan Chandel Sadhana, Springer Nature An efficient and novel FDTD method based performance investigation in high-speed current-mode signaling SWCNT bundle interconnect, vol. 43, no. 175, pp.1-12 SCIE
2019 Sunil Jadav, Rajeevan Chandel Analog Integrated Circuits and Signal Processing, Springer High performance 9T adiabatic SRAM and novel stability characterization using pole zero placement, vol. 98, no.2, pp. 347–355, February 2019 (SCI, Impact factor: 0.982) SCI
2020 Sunil Jadav, Rajeevan Chandel, M. Vashishath International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, Wiley, 33:e2698. https://doi. org/10.1002/jnm.2698 Modeling the Impact of Fundamental and Quantum Resistance on the Performance of SWCNT Based RLC Interconnects Scopus
2021 Neha Sharma, Rajeevan Chandel International Journal of Modeling, Simulation, and Scientific Computing Variation tolerant and stability simulation of low power SRAM cell analysis using FGMOS, 2150029 Scopus
2021 Animesh Srivastava, Rajeevan Chandel IETE Technical Review, Taylor & Francis Publication A Novel Co-planar Five Input Majority Gate Design in Quantum-Dot Cellular Automata, DOI: 10.1080/02564602.2021.1914205. SCIE
2021 Ashish Singh, Rajeevan Chandel, Rohit Dhiman Integration- the VLSI Journal, Elsevier Proposal and analysis of relative stability in mixed CNT bundle for sub-threshold interconnects, online 20 May SCIE
2021 Sunil Jadav, Shubham Tayal, Rajeevan Chandel, M. Vashishath Microelectronics Journal, Elsevier High speed RLC equivalent RC delay model using normalized asymptotic function for global VLSI interconnects, https://doi.org/10.1016/j.mejo.2020.104941, vol. 107, pp. 104941 SCIE, Scopus
2020 C. Ranga, A. Kumar, Rajeevan Chandel Insight-Non-Destructive Testing and Condition Monitoring Influence of electrical and thermal ageing on the mineral insulating oil performance for power transformer applications, vol. 62, no. 4, pp. 222-231, 2020. Scopus
2019 Sunil Jadav, Munish Vashistah, Rajeevan Chandel Analog Integrated Circuits and Signal Processing, Springer USA High speed RLC equivalent RC delay model for global VLSI interconnects, First Online: 22 January 2019. Doi:10.1007/s10470-019-01398-x, vol. 100, no.1, pp. 109–117, July 2019. SCI
2017 C. Ranga, Ashwani Kumar, and Rajeevan Chandel IET Science Measurements and Technology Condition assessment of power transformers based on multi-attributes using fuzzy logic, vol.11, no.8, pp. 983–990, 2017, July 2017 SCI
2017 Rohit Dhiman and Rajeevan Chandel Analog Integrated Circuits and Signal Processing Delay analysis of buffer inserted sub-threshold interconnects, vol. 90, no. 2, pp. 435-445, 2017. SCI
2017 Yash Agrawal, Rajeevan Chandel, and Rohit Dhiman IETE Journal of Research, Taylor & Francis Variability Analysis of Stochastic Parameters on the Electrical Performance of On-Chip Current-Mode Interconnect System, vol. 63, no.2, pp. 268-280, 2017. SCI
2018 C. Ranga, Ashwani Kumar, and R. Chandel IETE Technical Review, Taylor & Francis Performance analysis of alternative solid dielectrics of transformers with a blend of mineral and silicon oils, vol. 35, no. 4, pp. 331-341, 2018 SCIE
2016 V. Basetti, Ashwani Kumar Chandel, and Rajeevan Chandel Energy Power system dynamic state estimation using prediction based evolutionary technique, vol. 107, pp. 29-47, 2016. SCI
2016 Yash Agrawal, M. Girish Kumar, and Rajeevan Chandel IEEE Transactions on Nanotechnology A comprehensive model for high-speed current-mode signaling in next generation MWCNT bundle interconnect using FDTD technique, vol. 15, no. 4, pp. 590-598, 2016. DOI: 10.1109/TNANO.2016.2558475 SCI
2015 Rohit Dhiman, Rohit Sharma and Rajeevan Chandel Analog Integrated Circuits & Signal Processing, Springer, USA Compact models and delay computation of sub-threshold interconnect circuits, DOI 10.1007/s10470-015-0557-4, vol. 84, no.1, pp. 53-65, 2015 SCI
2015 Sunil Jadav, Munish Vashistah, Rajeevan Chandel International Journal of Modelling and Simulation, Taylor & Francis RLC equivalent RC delay model for global VLSI interconnect in current mode signalling, http://dx.doi.org/ 10.1080/02286203.2015.1077009, vol. 35, no. 1, pp. 27–34, 2015. Scopus
2021 Mekala Girish Kumar, Yash Agrawal, Vobulapuram Ramesh Kumar, Rajeevan Chandel Microelectronics Journal, Elsevier A prominent unified crosstalk model for linear and sub-threshold regions in mixed CNT bundle interconnects,” https://doi.org/10.1016/j.mejo.2021.105294, vol. 118, no.105294, pp. 1-11, 2021. SCIE, Scopus, IF=1.609
1994 Ashwani Kumar Chandel, Rajeevan Chandel and J.S. Saini ISTE Journal of Education, Enhancement of Placement Activities in Remotely Located Technical Institutes, vol. 17, no. 3, pp. 32-36, July-September, 1994. ISTE Pub.
2001 Rajeevan Chandel IETE Journal of Education “VLSI Micro-fabrication Technologies and MEMS, vol. 42, nos. 1-4, pp. 33-41, January-December 2001. Taylor & Francis Pub.
2007 Rajeevan Chandel VSI Vision, http://vlsi-india.org/ vsi/activities/events.html Design Techniques for VLSI and Communication DTVC-2007, vol. 3, no. 2, pp. 25, August 2007. VSI Pub.
2017 Chilaka Ranga, Ashwani Kumar and Rajeevan Chandel Journal of Renewable and Sustainable Energy, AIP Publishing Expert system for condition monitoring of power transformers using fuzzy logic, vol. 9, no. 4, pp. 1-16, July 2017. SCI
2016 M. Girish Kumar, Yash Agrawal, and Rajeevan Chandel IETE Journal of Education, Taylor & Francis Carbon nanotube interconnects—A Promising Solution for VLSI Circuits, DOI: 10.1080/09747338.2016.1158129, vol. 57, no. 2, pp. 46-64, 2016. T&F Publication
2016 Chilaka Ranga, Ashwani Kumar, and Rajeevan Chandel International Journal of Electrical Engineering and Informatics Fuzzy logic expert system for optimum maintenance of power transformers, International Journal of Electrical Engineering and Informatics, IJEEI, vol. 8, no. 4, pp. 836-850, September 2016. SCOPUS
2017 Chilaka Ranga, Ashwani Kumar, and Rajeevan Chandel International Journal of Electrical Engineering and Informatics, IJEEI Performance analysis of cellulose and Nomex impregnated oil filled power transformers, vol. 9, no. 2, pp. 394-406, July 2017. SCOPUS
2014 Philemon Daniel and Rajeevan Chandel Polish Journal of Electrical Review Przegląd Elektrotechniczny Dynamic Ruleset Based Online Concurrent Testing of Functional Faults for Embedded Controllers, ISSN 0033-2097, vol. 90, no. 1, pp. 111-114, 2014. Polish J.
2013 Viveka Paliwal, Rajeevan Chandel, S. Sarkar Journal of Active and Passive Electronic Devices (JAPED) New Noise Tolerance Improvement Techniques for Dynamic Logic Circuits, Vol.8, No.1, pp. 65-77, 2013. Old City Pub.
2012 Sandeep Singh Gill, Rajeevan Chandel, Ashwani K. Chandel International Journal of Artificial Intelligence and Soft Computing (IJAISC) Netlist Bipartitioning using Particle Swarm Optimization Technique, Vol. 3, No. 1, pp.1-15, 2012. Inderscience Pub.

Conference Publications


Year Author(s) Conference Title Indexing
2005 Rajeevan Chandel, S. Sarkar and R.P. Agarwal IEEE CANADIAN CONFERENCE on Electrical & Computer Engineering, CCECE 2005, Saskatoon, Canada On mitigating power and delay in VLSI interconnects, pp. 1533 - 1536 IEEE
1998 Rajeevan Chandel and Ashwani Kumar Chandel, “Sources of Environment Pollution and its Control in Rural Areas of HP”, Presented and Published in the Proceedings of the 28th ISTE Convention at PAU, Ludhiana, 21-23rd, Nov. 1998 Sources of Environment Pollution and its Control in Rural Areas of HP National
2020 Samarth Agarwal, A. Jamwal, A. Haider, P. Dev, Rajeevan Chandel 7th IEEE International Conference on Smart Structures and Systems (ICSSS 2020), Saveetha College of Engineering, 23rd & 24th July 2020. (BEST PAPER AWARD for the entire Session and Conference). Biometric Based Secured Remote Electronic Voting System. (BEST PAPER AWARD for the entire Session and Conference). IEEE
2020 Pawan Kumar Pandel, Dilip Singh, Rajeevan Chandel, Int. Conference on Microelectronics, Computing and Communication System (MCCS-2020) (Online), organized by IETE Advanced Regional Telecom Training Centre, BSNL Ranchi, Jharkhand, India, 11-12 July 2020. Fixed point division using Newton Raphson Algorithm,” Int. Conference on Microelectronics, Computing and Communication System (MCCS-2020) (Online), IETE International
2020 Animesh Srivastava, Rajeevan Chandel 1st International Conference on Communication, Computing and Signal Processing (CCSP-2020), NIT Jalandhar (Online), 23-24 July, 2020 Comparative Analysis of Cross Wired Implementation of Digital Function Design in QCA International
2018 Yash Agrawal, Rajeevan Chandel, Mekala Girish, and Rutu Parekh International IEEE Symposium on Electrical Design of Advanced Packaging and Systems (EDAPS-2018), Chandigarh, India, 16-18 Dec 2018 Contemporary On-chip System Modeling using FDTD in Low Power Regime IEEE
2018 Ashish Singh, Rohit Dhiman, and Rajeevan Chandel International IEEE Symposium on Electrical Design of Advanced Packaging and Systems (EDAPS-2018), Chandigarh, India, 16-18 Dec 2018 Modeling of Mixed CNT Bundle for Sub-threshold Interconnects IEEE
2018 Haritha Yeleti, Mekala Girish Kumar, Rajeevan Chandel, and Yash Agrawal International IEEE Symposium on Electrical Design of Advanced Packaging and Systems (EDAPS-2018), Chandigarh, India, 16-18 Dec 2018 Transient and Crosstalk Analysis of Doped and Dielectric Inserted MLGNR Interconnects IEEE
2017 Rajeevan Chandel, M. Girish Kumar International Conference on Emerging Trends in Engineering Innovations & Technology Management ICET: EITM-2017, NIT Hamirpur HP, pp. 381-385, 16-18 Dec 2017 Impact of Parameter Variability on Delay and Power Dissipation in Dielectric Inserted MLGNR Interconnects International
2021 Samarth Agarwal, Rajeevan Chandel International Conference on Recent Development on Materials, Reliability, Safety and Environmental Issues (IMRSE–2021), Dr. B R Ambedkar NIT Jalandhar, held from 25-27 June, 2021 A Comparative Study of Gallium Nitride Field Effect Transistors with Conventional Silicon Devices International
2021 Sonalika Singh, Rajeevan Chandel International Conference on Recent Development on Materials, Reliability, Safety and Environmental Issues (IMRSE–2021), Dr. B R Ambedkar NIT Jalandhar, held from 25-27 June, 2021 Design and Simulation of Low Noise Amplifier using Active Inductor for 100nm CMOS Technology International
2021 Afreen Haider and Rajeevan Chandel International Conference on Recent Development on Materials, Reliability, Safety and Environmental Issues (IMRSE–2021), Dr. B R Ambedkar NIT Jalandhar, held from 25-27 June, 2021 Design and Comparative Analysis of a Single Stage Differential Amplifier using FinFETs and MOSFETs International
2021 Razda Bisen, Rajeevan Chandel International Conference on Recent Development on Materials, Reliability, Safety and Environmental Issues (IMRSE–2021), Dr. B R Ambedkar NIT Jalandhar, held from 25-27 June, 2021 Machine Learning Usage for Decision Making in Automobile Sector International
2021 Samarth Agarwal & Rajeevan Chandel 10th International Symposium on Embedded Computing and System Design (ISED-2021), DA-IICT, Gandhinagar, Gujarat, 16th -18th July 2021. Energy Efficient SRAM Design Using FinFETs and Potential Alteration Topology Schemes International
2021 Nivali Yadav, Umesh Thakur, Akanksha Poonia, Rajeevan Chandel 8th IEEE International Conference on Signal Processing and Integrated Networks (SPIN-2021), DoE&CE, ASET, Amity University, Noida, Delhi-NCR, India, 26-27 August 2021 Post-Crash Detection and Traffic Analysis IEEE
2017 Gian Singh, Rajeevan Chandel, and Srishti Marwaha International Conference on Emerging Trends in Engineering Innovations & Technology Management ICET-EITM-17, NIT Hamirpur HP, pp. 446-449, 16-18 Dec 2017 Temperature Aware Dynamic Frequency Scaling Implementation in ARM Core Processor International
2017 Yash Agarwal, Rajeevan Chandel, and Ritu Parekh International Conference on Emerging Trends in Engineering Innovations & Technology Management ICET- EITM-17, NIT Hamirpur HP, pp. 374-380, 16-18 Dec 2017 Performance Evaluation of On-Chip Global Interconnects in DSM Technology using Different Signaling Techniques International
2017 Parmjit Singh, Rajeevan Chandel, and Neha Sharma IEEE International Conference on Contemporary Computing (IC3), Noida, India, pp. 1-6, 10-12 August, 2017 Stability Analysis of SRAM Cell designed using CNT and GNR Field Effect Transistors IEEE
2017 Neha Sharma and Rajeevan Chandel IEEE International Conference on Inventive Communication and Computing Technologies (ICICCT), Coimbatore, Tamil Nadu, India, pp. 160-165,10-11 March, 2017 Performance Analysis of SRAM Cell Designed using Floating Gate MOS IEEE
2021 Bharat K. Jangid, Dilip Singh, Rajeevan Chandel, Ashwani Rana 3rd IEEE International Conference on Innovations in Power & Advanced Computing Technologies (i-PACT2021), Vellore Institute of Technology, Vellore, Tamilnadu, India & University of Malaya (UM), Kuala Lumpur, Malaysia, Paper ID 448, 27-29, November 2021. A novel approach for Excitation codebook and Perceptual weighing Filter design. IEEE
2017 Parmjit Singh and Rajeevan Chandel IEEE International Conference on Inventive Communication and Computing Technologies, Coimbatore, Tamil Nadu, India, pp. 166-171,10-11 March, 2017. Design and Performance Analysis of Digital Circuits using Carbon Nanotube IEEE
2016 Sanjay S. Rajput, Ashish Singh, A.K. Chandel, and Rajeevan Chandel IEEE Computer Society Annual International Symposium on VLSI (ISVLSI), Pittsburg, USA, DOI: 10.1109/ISVLSI.2016.62, pp. 355-360, 11-13, July 2016, [DBLP]. Design of Low-Power High-Gain Operational Amplifier for Bio-Medical Applications IEEE
2016 Ramesh Kumar, Rohit Dhiman, Rajeevan Chandel IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), pp. 11-16, 2016. Performance analysis of Top-contact MLGNR Based Interconnects IEEE
2016 Neha Sharma and Rajeevan Chandel ISTE Section Annual Convention (SAC-2016), NIT Hamirpur, HP, India, 30th Sep -2st Oct, 2016. Simulation and Analysis of Low Power Floating Gate MOS Inverter using Tanner EDA ISTE
2015 Yash Agrawal, Rajeevan Chandel, M. Girish Kumar IEEE International Symposium on Nanoelectronic and Information Systems (iNIS’15), Indore, India, pp. 297-302, 21-23 Dec 2015. Performance Analysis of Multilayer Graphene Nano-Ribbon in Current-Mode Signaling Interconnect System IEEE
2015 Girish Kumar, Rajeevan Chandel, Yash Agrawal IEEE International Symposium on Nanoelectronic and Information Systems (iNIS’15), Indore, India, pp. 308 – 313, 21-23 Dec 2015. Timing and Stability Analysis of Carbon nanotube Interconnects IEEE
2015 Rahul Kumar, Rohit Dhiman, Rajeevan Chandel National ISTE Section Annual Convention, NIT Hamirpur, 30 Sep –1 Oct, 2015. Low Power, Low Voltage, High Performance Analog Circuits Using FGMOS Transistors-An Overview ISTE
2015 Ashish Singh, Rajeevan Chandel National ISTE Section Annual Convention, NIT Hamirpur, 30 Sep –1 Oct, 2015. Low Dropout Voltage Regulator ISTE