profile
Dr. Rohit Dhiman
Assistant ProfessorRohit Dhiman received his B.Tech. in Electronics & Communication Engineering from HP University Shimla, India in 2007. He did his M.Tech. Degree in VLSI Design from National Institute of Technology (NIT) Hamirpur in 2009. He was awarded Ph.D. Degree from NIT Hamirpur in 2014. Presently Dr. Rohit Dhiman is working as an Assistant Professor in Electronics & Communication Engineering Department at NIT Hamirpur and is the author/co-author of reputed publications in Journals and Conference proceedings of repute. He has been awarded Young Scientist Award from the Department of Science & Technology, Science and Engineering Research Board, GoI, New Delhi. He has also been granted with the prestigious Young Faculty Research Fellowship from the Ministry of Electronics and Information Technology (MeitY), Govt. of India and has three sponsored research projects to his credit. His major research interest is in device and circuit modelling for low power nanoscale IC design.
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General Information
| Name | : | Dr. Rohit Dhiman |
| Designation | : | Assistant Professor |
| Department | : | Electronics & Communication Engineering |
| Qualification | : | PhD |
| Date of Birth | : | |
| Date of joining | : |
Contact Details
| Phone | : | 01972 |
| Email ID | : | rohitdhiman@nith.ac.in |
Specialization
Position Held
| Position | Department Name | Institute Name | Time Period |
|---|
Educational Qualification
| Name of the Degree | Year of Passing | Institute/University |
|---|---|---|
| Doctor of Philosophy (Ph.D.) | 2014 | National Institute of Technology (NIT) Hamirpur (HP) |
| Master of Technology (M.Tech.) | 2009 | National Institute of Technology (NIT) Hamirpur (HP) |
| Bachelor of Technology (B.Tech.) | 2007 | HP University, Shimla |
Honors & Recognitions Achieved
| Sr.No. | Title | Activity | Given By | Year |
|---|---|---|---|---|
| 1 | Young Faculty Research Fellowship | Research | MeitY (GoI) | 2019 |
| 2 | 3rd Position in Intel Rapid Prototyping Camp, 2017 | Research | INTEL | 2017 |
Research Experience
| Research Interests : | VLSI & Post-CMOS Devices, Circuits and their Modeling | |
| Brief Research Statement : |
Journal Publications
| Year | Author(s) | Title & Vol. No. | Journal Name | Indexing (SCI) Web of Science/Scopus |
|---|---|---|---|---|
| 2019 | Ashish Singh and Rohit Dhiman | Proposal and analysis of mixed CNT bundle for sub-threshold interconnects | IEEE Transactions on Nanotechnology | SCI |
| 2019 | Anchal Thakur and Rohit Dhiman | SiGe/ Si hetero nanotube JLFET for improved performance: Proposal and investigation | IET Electronics Letters | SCI |
| 2021 | Ashish Singh, Rajeevan Chandel and Rohit Dhiman | Proposal and analysis of relative stability in mixed CNT bundle for sub-threshold interconnects | INTEGRATION, the VLSI Journal (Elsevier) | SCI |
| 2021 | Anchal Thakur and Rohit Dhiman | Temperature assessment of Si1−xGex source/ drain heterojunction NT JLFET for gate induced drain leakage–A compact model | Superlattices and Microstructures (Elsevier) | SCI |
Conference Publications
| Year | Author(s) | Title | Conference name with place | Indexing (SCI/Web of science/Scopus) |
|---|---|---|---|---|
| 2016 | A. Shrivastava, A. Gangwar, R. Kumar, and Rohit Dhiman | A 60 dB bulk-driven rail-to-rail input/output OTA | IEEE International Symposium on Nanoelectronic and Information Systems | IEEE/ Scopus |
| 2016 | R. Kumar, Rohit Dhiman, and R. Chandel | Performance analysis of top-contact MLGNR based interconnects | IEEE International Symposium on Nanoelectronic and Information Systems | IEEE/ Scopus |
| 2018 | Ashish Singh and Rohit Dhiman | Modeling of mixed CNT bundle for sub-threshold interconnects | IEEE Electrical Design of Advanced Packaging and Systems Symposium (IEEE-EDAPS), IIT Ropar (Pb) | IEEE/ Scopus |
| 2019 | Anchal Thakur and Rohit Dhiman | Design and performance analysis of SiGe source-drain hetero-structure nanotube junctionless FET | IEEE TENCON | IEEE/ Scopus |
| 2021 | Palak Sood and Rohit Dhiman | Brain-Computer Interfacing: Design of Virtual Keyboard | 12th INTERNATIONAL CONFERENCE ON COMPUTING, COMMUNICATION AND NETWORKING TECHNOLOGIES, IIT Khargpur (WB) | Scopus |
Research Projects
| Role | Project Type | Title | Funding Agency | From | To | Amount | Status | Co-Investigator | Sanction Order | Sanction Date |
|---|---|---|---|---|---|---|---|---|---|---|
| Principal Investigator | External Sponsored | Ultra-low Power Performance Investigations in Carbon Nano-tube based Interconnects (Young Scientist Scheme) | Science and Engineering Research Board, Department of Science and Technology (GoI), New Delhi | 20/08/2016 | 19/08/2019 | Rs. 13,95,680/- | Completed | None | YSS/2015/001122 | 25/07/2016 |
| Young Faculty Research Fellow | External Sponsored | Young Faculty Research Fellowship (YFRF) | Ministry of Electronics and Information Technology (MeitY), GoI | 18/12/2019 | 17/12/2022 | Rs. 37 Lakhs | On-going | None | DIC/MUM/GA/10(37)E | 07/11/2019 |
| Principal Investigator | External Sponsored | Through Package Vias in GI for Heterogeneous Three-Dimensional Integration | Science and Engineering Research Board, Department of Science and Technology (GoI), New Delhi | 28/01/2022 | 27/01/2025 | Rs. 18 Lakh | On-going | None | CRG/2021/000780 | 21/01/2022 |
| Co-Chief Investigator | External Sponsored | SMDP-C2SD | Ministry of Electronics and Information Technology (MeitY), GoI | 24/09/2020 | 30/11/2021 | Rs. 93 Lakh | Completed | Dr. Ashwani Kumar Rana | NIT/HMR/R&C/28/2020 | 24/09/2020 |
| Mentor | External Sponsored | IoT Enabled Energy Management System: Design and Implementation | Department of Science and Technology | 14/02/2017 | 13/02/2018 | Rs. 100000/- | Completed | None | File No. NIT/HMR/TEQIP-II/R&D-19/2017/21-30 | 14/02/2017 |
Research Supervision
| Programme Name | Scholar Name | Research Topic | Status | Year | Co-Suprivisor(s) |
|---|---|---|---|---|---|
| Ph.D | Anchal Thakur | Performance Investigations in Nanotube Junctionless Field Effect Transistor from GIDL and Reliability Perspectives | Awarded | 2021 | |
| Ph.D | Ashish Singh | Study of Mixed Carbon Nanotube Bundles for VLSI Interconnects in Sub-threshold Regime | Awarded | 2022 | |
| Ph.D | Ajay Kumar | Electrical Characterization of Through Packaging Vias for Three-Dimensional Integration | On-going | 2019 | |
| Ph.D | Sachindra Bharti | Novel Junctionless Field-effect Transistor for Low Power ICs | Ongoing | 2020 | Dr. Gargi Khanna |
| Ph.D | K. Madhu Kiran | Through Package Vias in Glass and Silicon Interposers for Heterogeneous Three-Dimensional Integration | On-going | 2022 |
Patents
| Title | Reg./Ref.No. | Date of Award/Filling | Awarding Agencies | Status |
|---|---|---|---|---|
| Method and System for Enriching Life in a Humanly Maintained Aquaculture Environment | 2018xx7x95A | 13/06/2022 | Office of the Controller General of Patents, Designs& Trade marks, Govt of India | Awarded |
Teaching Experience
| Position Held | Department and Organization | From | To | Total Experience |
|---|---|---|---|---|
| Lecturer | ECE Department, National Institute of Technology, Hamirpur (HP) | 19/07/2010 | 14/07/2015 | 5 Years (Approx.) |
| Assistant Professor (Grade-II) | ECE Department, National Institute of Technology, Hamirpur (HP) | 14/07/2015 | 06/05/2019 | 3years & 10 Months |
| Assistant Professor (Grade-I) | ECE Department, National Institute of Technology, Hamirpur (HP) | 06/05/2019 | Present |
Administrative Experience
| Position Held | Department and Organization | From | To |
|---|---|---|---|
| Faculty In-charge, Cultural & Technical Activities | Student Welfare Section | 01/05/2020 | 21/06/2021 |
| Convener DBPC | E&CE Department | 21/08/2019 | 10/10/2022 |
| Convener DMPC | E&CE Department | 11/10/2022 | |
| Assistant Warden | Neelkanth Boys Hostel | 25/03/2019 | 31/05/2020 |
| Nodal Officer [OBC cell] | Dean (FW) | 01/05/2019 | 30/04/2020 |
| Liaison Officer [Reservation Cell – OBC & EWS] | Dean (FW) | 01/05/2020 | |
| Faculty Incharge: Technical Activities | Student Welfare Section | 21/06/2021 | 07/10/2022 |
| Assistant Warden | Dhauladhar Boys Hostel | 27/07/2015 | 28/09/2017 |
Book/Chapters Written
| Type | Title | Publisher | Author(s) | ISBN/ISSN No. | Year |
|---|---|---|---|---|---|
| Book | Nanoelectronics for Next-Generation Integrated Circuits | CRC Press, Boca Raton, New York, USA | Rohit Dhiman | 9780367726522 | 2022 |
| Book | VLSI and Post-CMOS Electronics: Design, Modelling and Simulation (Vol. I) | Institution of Engineering and Technology (IET), Stevenage Herts, London, UK | Rohit Dhiman and Rajeevan Chandel | 978-1-83953-051-7 | 2019 |
| Book | VLSI and Post-CMOS Electronics: Devices, Circuits and Interconnects (Vol. II) | Institution of Engineering and Technology (IET), Stevenage Herts, London, UK | Rohit Dhiman and Rajeevan Chandel | 978-1-83953-053-1 | 2019 |
| Book | Nanoscale VLSI: Devices, Circuits, and Applications | Springer Nature, Singapore | Rohit Dhiman and Rajeevan Chandel | 978-981-15-7936-3 | 2020 |
| Book | Emerging Nano-FETs: Design, Modeling, and Performance | Springer Nature, Singapore | Rohit Dhiman | Upcoming | 2023 |
Expert Talks
| Title | Place | Year | Description of Event |
|---|
Consultancy
| Title of Consultancy | Client Organization | Faculty Involved | Amount(INR) | Status |
|---|
International and National Exposure
| Sr.No. | Title | Description |
|---|
Conferences/Courses Organized
| Category | Type | Title | Venue | From | To | Designation |
|---|---|---|---|---|---|---|
| workshop | SERB Sponsored Workshop | VLSI Design and IC Packaging Techniques | NIT Hamirpur | 21/12/2022 | 21/12/2022 | Coordinator |
| stc | Electronics & ICT Academy, IIT Roorkee | VLSI Chip Design Hands-on Using Open Source EDA | NIT Hamirpur | 08/07/2019 | 12/07/2019 | Coordinator |
| stc | STC under SDF (Seed Money) | EDA Tools for Electronic System Design | NIT Hamirpur | 01/01/2018 | 06/01/2018 | Convener |
| stc | STC under Skill India Program | Repair and Effective use of Electronic Equipment | NIT Hamirpur | 30/10/2017 | 04/11/2017 | Coordinator |
| conference | National Conference | VLSI, Signal Processing and Communication Engineering | NIT Hamirpur | 16/08/2017 | 17/08/2017 | Joint Secretary |
| stc | STC | Advances in Design Techniques for Low Power VLSI and MEMS Systems | NIT Hamirpur | 18/07/2016 | 23/07/2016 | Coordinator |
| stc | STC | Recent Trends in VLSI and Communication Systems | NIT Hamirpur | 10/06/2013 | 14/06/2013 | Co-Coordinator |
| conference | STC | Embedded System and HDL | NIT Hamirpur | 20/05/2013 | 24/05/2013 | Co-Coordinator |
Profile Summary
Last Update: 02/04/2023 11:16pm
| Name | : | Dr. Rohit Dhiman |
| Designation | : | Assistant Professor |
| Department | : | Electronics & Communication Engineering |
| Qualification | : | PhD |
| Phone | : | 01972 |
| Email ID | : | rohitdhiman@nith.ac.in |
| Profile URL | : | https://portfolios.nith.ac.in/index.php?/nith/rohit-dhiman |
| Date of Birth | : | |
| Date of Joining | : |
Specialization
Electronics and Communication
Education Qualification
| Name of the Degree | Year of Passing | Institute/University |
|---|---|---|
| Doctor of Philosophy (Ph.D.) | 2014 | National Institute of Technology (NIT) Hamirpur (HP) |
| Master of Technology (M.Tech.) | 2009 | National Institute of Technology (NIT) Hamirpur (HP) |
| Bachelor of Technology (B.Tech.) | 2007 | HP University, Shimla |
Teaching Experience
| Programme Name | Department And Organization | From | To | Total Experience |
|---|---|---|---|---|
| Lecturer | ECE Department, National Institute of Technology, Hamirpur (HP) | 19/07/2010 | 14/07/2015 | 5 Years (Approx.) |
| Assistant Professor (Grade-II) | ECE Department, National Institute of Technology, Hamirpur (HP) | 14/07/2015 | 06/05/2019 | 3years & 10 Months |
| Assistant Professor (Grade-I) | ECE Department, National Institute of Technology, Hamirpur (HP) | 06/05/2019 | Present |
Administrative Experience
| Position Held | Department And Organization | From | To |
|---|---|---|---|
| Faculty In-charge, Cultural & Technical Activities | Student Welfare Section | 01/05/2020 | 21/06/2021 |
| Convener DBPC | E&CE Department | 21/08/2019 | 10/10/2022 |
| Convener DMPC | E&CE Department | 11/10/2022 | |
| Assistant Warden | Neelkanth Boys Hostel | 25/03/2019 | 31/05/2020 |
| Nodal Officer [OBC cell] | Dean (FW) | 01/05/2019 | 30/04/2020 |
| Liaison Officer [Reservation Cell – OBC & EWS] | Dean (FW) | 01/05/2020 | |
| Faculty Incharge: Technical Activities | Student Welfare Section | 21/06/2021 | 07/10/2022 |
| Assistant Warden | Dhauladhar Boys Hostel | 27/07/2015 | 28/09/2017 |
Research Experience
| Research Interests : | VLSI & Post-CMOS Devices, Circuits and their Modeling | |
| Brief Research Statement : |
Research Projects
| Role | Project Type | Title | Funding Agency | From | To | Amount | Status | Co-Investigator | Sanction Order | Sanction Date |
|---|---|---|---|---|---|---|---|---|---|---|
| Principal Investigator | External Sponsored | Ultra-low Power Performance Investigations in Carbon Nano-tube based Interconnects (Young Scientist Scheme) | Science and Engineering Research Board, Department of Science and Technology (GoI), New Delhi | 20/08/2016 | 19/08/2019 | Rs. 13,95,680/- | Completed | None | YSS/2015/001122 | 25/07/2016 |
| Young Faculty Research Fellow | External Sponsored | Young Faculty Research Fellowship (YFRF) | Ministry of Electronics and Information Technology (MeitY), GoI | 18/12/2019 | 17/12/2022 | Rs. 37 Lakhs | On-going | None | DIC/MUM/GA/10(37)E | 07/11/2019 |
| Principal Investigator | External Sponsored | Through Package Vias in GI for Heterogeneous Three-Dimensional Integration | Science and Engineering Research Board, Department of Science and Technology (GoI), New Delhi | 28/01/2022 | 27/01/2025 | Rs. 18 Lakh | On-going | None | CRG/2021/000780 | 21/01/2022 |
| Co-Chief Investigator | External Sponsored | SMDP-C2SD | Ministry of Electronics and Information Technology (MeitY), GoI | 24/09/2020 | 30/11/2021 | Rs. 93 Lakh | Completed | Dr. Ashwani Kumar Rana | NIT/HMR/R&C/28/2020 | 24/09/2020 |
| Mentor | External Sponsored | IoT Enabled Energy Management System: Design and Implementation | Department of Science and Technology | 14/02/2017 | 13/02/2018 | Rs. 100000/- | Completed | None | File No. NIT/HMR/TEQIP-II/R&D-19/2017/21-30 | 14/02/2017 |
Journal Publications
| Year | Author(s) | Journal Name | Title & Vol. No. | Indexing (SCI/Web of science/Scopus) |
|---|---|---|---|---|
| 2019 | Ashish Singh and Rohit Dhiman | IEEE Transactions on Nanotechnology | Proposal and analysis of mixed CNT bundle for sub-threshold interconnects | SCI |
| 2019 | Anchal Thakur and Rohit Dhiman | IET Electronics Letters | SiGe/ Si hetero nanotube JLFET for improved performance: Proposal and investigation | SCI |
| 2021 | Ashish Singh, Rajeevan Chandel and Rohit Dhiman | INTEGRATION, the VLSI Journal (Elsevier) | Proposal and analysis of relative stability in mixed CNT bundle for sub-threshold interconnects | SCI |
| 2021 | Anchal Thakur and Rohit Dhiman | Superlattices and Microstructures (Elsevier) | Temperature assessment of Si1−xGex source/ drain heterojunction NT JLFET for gate induced drain leakage–A compact model | SCI |
Conference Publications
| Year | Author(s) | Conference | Title | Indexing |
|---|---|---|---|---|
| 2016 | A. Shrivastava, A. Gangwar, R. Kumar, and Rohit Dhiman | IEEE International Symposium on Nanoelectronic and Information Systems | A 60 dB bulk-driven rail-to-rail input/output OTA | IEEE/ Scopus |
| 2016 | R. Kumar, Rohit Dhiman, and R. Chandel | IEEE International Symposium on Nanoelectronic and Information Systems | Performance analysis of top-contact MLGNR based interconnects | IEEE/ Scopus |
| 2018 | Ashish Singh and Rohit Dhiman | IEEE Electrical Design of Advanced Packaging and Systems Symposium (IEEE-EDAPS), IIT Ropar (Pb) | Modeling of mixed CNT bundle for sub-threshold interconnects | IEEE/ Scopus |
| 2019 | Anchal Thakur and Rohit Dhiman | IEEE TENCON | Design and performance analysis of SiGe source-drain hetero-structure nanotube junctionless FET | IEEE/ Scopus |
| 2021 | Palak Sood and Rohit Dhiman | 12th INTERNATIONAL CONFERENCE ON COMPUTING, COMMUNICATION AND NETWORKING TECHNOLOGIES, IIT Khargpur (WB) | Brain-Computer Interfacing: Design of Virtual Keyboard | Scopus |
Book/Chapters Written
| Type (Book/Chapter) | Author(s) | Title | Publisher | ISBN/ISSN No. | Year |
|---|---|---|---|---|---|
| Book | Rohit Dhiman | Nanoelectronics for Next-Generation Integrated Circuits | CRC Press, Boca Raton, New York, USA | 9780367726522 | 2022 |
| Book | Rohit Dhiman and Rajeevan Chandel | VLSI and Post-CMOS Electronics: Design, Modelling and Simulation (Vol. I) | Institution of Engineering and Technology (IET), Stevenage Herts, London, UK | 978-1-83953-051-7 | 2019 |
| Book | Rohit Dhiman and Rajeevan Chandel | VLSI and Post-CMOS Electronics: Devices, Circuits and Interconnects (Vol. II) | Institution of Engineering and Technology (IET), Stevenage Herts, London, UK | 978-1-83953-053-1 | 2019 |
| Book | Rohit Dhiman and Rajeevan Chandel | Nanoscale VLSI: Devices, Circuits, and Applications | Springer Nature, Singapore | 978-981-15-7936-3 | 2020 |
| Book | Rohit Dhiman | Emerging Nano-FETs: Design, Modeling, and Performance | Springer Nature, Singapore | Upcoming | 2023 |
Research Supersion
| Programme Name | Scholar Name | Research Topic | Status | Year | Co-Superivisor(s) |
|---|---|---|---|---|---|
| Ph.D | Anchal Thakur | Performance Investigations in Nanotube Junctionless Field Effect Transistor from GIDL and Reliability Perspectives | Awarded | 2021 | |
| Ph.D | Ashish Singh | Study of Mixed Carbon Nanotube Bundles for VLSI Interconnects in Sub-threshold Regime | Awarded | 2022 | |
| Ph.D | Ajay Kumar | Electrical Characterization of Through Packaging Vias for Three-Dimensional Integration | On-going | 2019 | |
| Ph.D | Sachindra Bharti | Novel Junctionless Field-effect Transistor for Low Power ICs | Ongoing | 2020 | Dr. Gargi Khanna |
| Ph.D | K. Madhu Kiran | Through Package Vias in Glass and Silicon Interposers for Heterogeneous Three-Dimensional Integration | On-going | 2022 |
Patents
| Name | Reg./Ref.No. | Date of Award/Filling | Awarding Agencies | Status |
|---|---|---|---|---|
| Method and System for Enriching Life in a Humanly Maintained Aquaculture Environment | 2018xx7x95A | 13/06/2022 | Office of the Controller General of Patents, Designs& Trade marks, Govt of India | Awarded |
Conferences/Workshop/Courses Organized
| Category | Type | Title | Venue | From | To | Designation |
|---|---|---|---|---|---|---|
| workshop | SERB Sponsored Workshop | VLSI Design and IC Packaging Techniques | NIT Hamirpur | 21/12/2022 | 21/12/2022 | Coordinator |
| stc | Electronics & ICT Academy, IIT Roorkee | VLSI Chip Design Hands-on Using Open Source EDA | NIT Hamirpur | 08/07/2019 | 12/07/2019 | Coordinator |
| stc | STC under SDF (Seed Money) | EDA Tools for Electronic System Design | NIT Hamirpur | 01/01/2018 | 06/01/2018 | Convener |
| stc | STC under Skill India Program | Repair and Effective use of Electronic Equipment | NIT Hamirpur | 30/10/2017 | 04/11/2017 | Coordinator |
| conference | National Conference | VLSI, Signal Processing and Communication Engineering | NIT Hamirpur | 16/08/2017 | 17/08/2017 | Joint Secretary |
| stc | STC | Advances in Design Techniques for Low Power VLSI and MEMS Systems | NIT Hamirpur | 18/07/2016 | 23/07/2016 | Coordinator |
| stc | STC | Recent Trends in VLSI and Communication Systems | NIT Hamirpur | 10/06/2013 | 14/06/2013 | Co-Coordinator |
| conference | STC | Embedded System and HDL | NIT Hamirpur | 20/05/2013 | 24/05/2013 | Co-Coordinator |
Expert Talks
| Title | Place | Year | Description of Event |
|---|
Consultancy
| Title of Consultancy | Client Organization | Faculty Involved | Amount(INR) | Status |
|---|
International and National Exposure
| Sr.No. | Title | Description |
|---|
Honors & Recognitions Achieved
| Sr.No. | Title | Activity | Given By | Year |
|---|---|---|---|---|
| 1 | Young Faculty Research Fellowship | Research | MeitY (GoI) | 2019 |
| 2 | 3rd Position in Intel Rapid Prototyping Camp, 2017 | Research | INTEL | 2017 |